General-purpose
RDRAND
RDRAND returns random numbers from a generator in the processor that its hardware entropy source keeps reseeding.
- CPUID
- RDRAND
CPUID.01H:ECX[30] - Instructions
- 1 mnemonic
- Processors
- Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
- Linux flag
rdrand
RDRAND returns a 16-, 32- or 64-bit random number from a deterministic random bit generator in the processor (built to NIST SP 800-90A), which an on-chip entropy source reseeds frequently. It sets CF when the value is valid. When many cores ask at once, or when the generator’s self-test rejects a value, CF is clear and the destination zero; Intel recommends retrying a limited number of times, such as ten, rather than looping forever.
For seeding a generator of one’s own, RDSEED gives access to the entropy source itself. RDRAND came with Intel’s Ivy Bridge and AMD’s Excavator.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| RDRAND | Returns a random number from the processor's hardware generator; CF=1 means the value is valid, CF=0 that none was ready. | 1 |
CPUID and processors
XED splits RDRAND into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors in XED |
|---|---|---|
RDRAND | RDRAND | Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2 |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.