CPUID
RDTSCP
CPUID.80000001H:EDX[27]
Instructions
1 mnemonic
Processors
Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2

RDTSCP reads the time-stamp counter into EDX:EAX, as RDTSC does, and also the IA32_TSC_AUX MSR into ECX. Operating systems store the processor’s number there (Linux its CPU and NUMA node numbers), so a program learns which processor the time stamp came from.

RDTSCP waits until all earlier instructions have executed and their loads are globally visible, so the code being measured is not cut short; later instructions may still start before it. It is enumerated in CPUID.80000001H:EDX[27]. RDPID reads IA32_TSC_AUX alone.

Instructions

Mnemonics with at least one form in RDTSCP. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
RDTSCPReads the time-stamp counter into EDX:EAX and IA32_TSC_AUX into ECX, once all earlier instructions have executed.1

CPUID and processors

XED splits RDTSCP into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of RDTSCP. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  4. Linux arch/x86/include/asm/segment.h: the CPU and node number in IA32_TSC_AUX

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.