Memory, caches and atomics
RTM
Restricted Transactional Memory: XBEGIN starts a transaction whose memory updates all become visible on XEND, or are all rolled back on a conflict or an abort.
- CPUID
- RTM
CPUID.(EAX=07H,ECX=0):EBX[11] - Instructions
- 4 mnemonics
- Processors
- Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
Restricted Transactional Memory runs a region of code as a transaction. XBEGIN starts it and names a fallback address; the region’s stores stay invisible to other cores until XEND commits them all at once. If another core touches the same data, the transaction runs out of resources, or the code executes XABORT or an instruction that always aborts, the processor discards everything the region did and jumps to the fallback address with the reason in EAX. XTEST tells whether code is running in a transaction.
The fallback path usually takes a lock, so RTM speeds up locking where threads rarely conflict. Intel’s manual defines a CPUID bit, RTM_ALWAYS_ABORT, for processors on which every XBEGIN aborts at once; software must work that way too. TSXLDTRK extends RTM.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| XABORT | Aborts an RTM transaction, discarding its effects and resuming at the XBEGIN fallback with an 8-bit reason code in EAX. | 1 |
| XBEGIN | Starts an RTM transaction; if it aborts, its effects are rolled back and execution goes to the fallback address, with the reason in EAX. | 1 |
| XEND | Commits an RTM transaction, making all of its memory updates visible at once. | 1 |
| XTEST | Clears ZF inside an RTM or HLE transaction and sets it outside one. | 1 |
CPUID and processors
XED splits RTM into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors |
|---|---|---|
RTM | RTM | Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.