x86-64.net

Cryptography

SHA

The SHA extensions compute rounds and message schedules of SHA-1 and SHA-256 on XMM registers.

CPUID
SHA
CPUID.(EAX=07H,ECX=0):EBX[29]
Instructions
7 mnemonics
Processors
Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
Linux flag
sha_ni

The SHA extensions accelerate SHA-1 and SHA-256. For each hash, two instructions compute the message schedule and one performs rounds: SHA1RNDS4 does four rounds of SHA-1, with SHA1NEXTE preparing the next state value, and SHA256RNDS2 does two rounds of SHA-256, reading the message words and round constants from XMM0. They came with Intel’s Goldmont Atoms and AMD’s Zen, and reached Intel’s large cores later. SHA-512 has instructions of its own, in SHA512.

Instructions

Mnemonics with at least one form in SHA. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
SHA1MSG1Performs the first step of the SHA-1 message schedule, an XOR of message dwords, for the next four.2
SHA1MSG2Performs the second step of the SHA-1 message schedule, finishing four message dwords with a rotate.2
SHA1NEXTEComputes the SHA-1 state variable E after four rounds from the state and adds it to the next four message dwords.2
SHA1RNDS4Performs four rounds of SHA-1, with the round function and constant chosen by an immediate.2
SHA256MSG1Performs the first step of the SHA-256 message schedule for the next four message dwords.2
SHA256MSG2Performs the second step of the SHA-256 message schedule, finishing four message dwords.2
SHA256RNDS2Performs two rounds of SHA-256, taking the message words plus round constants from XMM0.2

CPUID and processors

XED splits SHA into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SHA. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SHA

SHA
CPUID.(EAX=07H,ECX=0):EBX[29] SHA

Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.