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Cryptography

SHA512

VEX-encoded message schedule and round instructions for SHA-384 and SHA-512.

CPUID
SHA512 + AVX
CPUID.(EAX=07H,ECX=1):EAX[0]
CPUID.01H:ECX[28]
Instructions
3 mnemonics
Processors
Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest

SHA512 accelerates the SHA-512 hash of FIPS 180-4 on 256-bit VEX registers, the counterpart of the older SHA extension for SHA-1 and SHA-256. VSHA512RNDS2 performs two rounds: the eight 64-bit state words are split across two YMM registers, and an XMM register supplies two message words already added to their round constants. VSHA512MSG1 and VSHA512MSG2 compute the message schedule four words at a time. The instructions need both the SHA512 feature bit and AVX.

Instructions

Mnemonics with at least one form in SHA512. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VSHA512MSG1Performs the first half of the SHA-512 message schedule computation for the next four message quadwords.1
VSHA512MSG2Completes the SHA-512 message schedule computation for the next four message quadwords.1
VSHA512RNDS2Performs two rounds of SHA-512 (and SHA-384) on the working state, using precomputed message and round-constant sums.1

CPUID and processors

XED splits SHA512 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SHA512. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
SHA512

SHA512 + AVX
CPUID.(EAX=07H,ECX=1):EAX[0] SHA512
CPUID.01H:ECX[28] AVX

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.