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Cryptography

SM3

VEX-encoded message expansion and round instructions for the SM3 hash function.

CPUID
SM3 + AVX
CPUID.(EAX=07H,ECX=1):EAX[1]
CPUID.01H:ECX[28]
Instructions
3 mnemonics
Processors
Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest

SM3 accelerates the SM3 hash function, a Chinese national standard (GB/T 32905-2016) with a 256-bit digest. VSM3RNDS2 performs two rounds, with the state split across two XMM registers and the immediate giving the (even) round number, which selects the round constant. VSM3MSG1 and VSM3MSG2 compute the message expansion. The instructions need both the SM3 feature bit and AVX.

Instructions

Mnemonics with at least one form in SM3. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VSM3MSG1Performs the first part of the SM3 message expansion for the next four message words.2
VSM3MSG2Completes the SM3 message expansion for the next four message words.2
VSM3RNDS2Performs two rounds of the SM3 hash function, starting at the round number in an immediate.2

CPUID and processors

XED splits SM3 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SM3. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
SM3

SM3 + AVX
CPUID.(EAX=07H,ECX=1):EAX[1] SM3
CPUID.01H:ECX[28] AVX

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. IETF draft-sca-cfrg-sm3-02: The SM3 Cryptographic Hash Function (January 2018)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.