x86-64.net

System

SMAP

Supervisor Mode Access Prevention stops the kernel from reading or writing user pages, unless it sets the AC flag with STAC for the access and clears it again with CLAC.

CPUID
SMAP
CPUID.(EAX=07H,ECX=0):EBX[20]
Instructions
2 mnemonics
Processors
Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

With Supervisor Mode Access Prevention enabled (CR4.SMAP), kernel code that reads or writes a page of user memory faults, which turns many kernel bugs that follow a user-supplied pointer into crashes instead of exploits. The kernel still has to copy data to and from user memory on purpose, so SMAP lets those accesses through while the AC flag is set: STAC sets it before such a copy and CLAC clears it after. Both run only at privilege level 0, where the flag otherwise has no use. SMEP, its companion, stops the kernel from executing user pages and needs no instructions.

Instructions

Mnemonics with at least one form in SMAP. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CLACClears the alignment-check flag (AC), so that SMAP again stops the kernel from touching user pages; ring 0 only.1
STACSets the alignment-check flag (AC), which lets the kernel reach user pages despite SMAP until CLAC clears it; ring 0 only.1

CPUID and processors

XED splits SMAP into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SMAP. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SMAP

SMAP
CPUID.(EAX=07H,ECX=0):EBX[20] SMAP

Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.