x86-64.net

System

SMX (Intel TXT) instructions

SMX, the Safer Mode Extensions behind Intel TXT, adds GETSEC, whose leaf functions launch a measured environment from code that the processor has authenticated.

CPUID
SMX
CPUID.01H:ECX[6]
Instructions
1 mnemonic
Processors
Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill

Instructions

Mnemonics with at least one form in SMX. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
GETSECPerforms the Safer Mode Extensions leaf function that EAX selects, such as SENTER, which launches an Intel TXT measured environment.1

Leaf functions

The operations that these instructions select by the value of a register, each with a page of its own.

EAXLeaf functionSummary
00HGETSEC[CAPABILITIES]Returns a bit for each GETSEC leaf the processor supports and one for an Intel TXT chipset; any privilege level may run it.
02HGETSEC[ENTERACCS]Loads the authenticated code module at the physical address in EBX, checks its signature with the chipset's key and runs it.
03HGETSEC[EXITAC]Leaves authenticated code execution mode and continues at the address in EBX; an authenticated code module ends with it.
04HGETSEC[SENTER]Launches a measured environment: authenticates the module at the physical address in EBX and gathers the other logical processors.
05HGETSEC[SEXIT]Ends the measured environment that SENTER launched, signalling every logical processor of the platform.
06HGETSEC[PARAMETERS]Returns one SMX parameter per index in EBX, such as the versions of authenticated code modules that the processor accepts.
07HGETSEC[SMCTRL]Performs the SMX mode control that EBX selects; the only one, 0, unmasks SMIs after a measured launch.
08HGETSEC[WAKEUP]Wakes the other logical processors from the sleep state that the SENTER rendezvous left them in, so that they join the measured environment.

CPUID and processors

XED splits SMX into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SMX. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SMX

SMX
CPUID.01H:ECX[6] SMX

Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill

Note: XED's AMD chips, which it derives from its Intel chips, have SMX too; AMD processors do not implement GETSEC, so this list leaves them out.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.