SSE instruction set extension

SSE added a separate register file for vector arithmetic to x86: eight 128-bit XMM registers, 16 in 64-bit mode, and the MXCSR register for rounding control and exception flags. Its instructions work on four packed singles or on the low single alone (the “PS” and “SS” forms), and it also brought prefetch hints, SFENCE and a few integer instructions for MMX registers. The operating system has to save the new state, which it signals with CR4.OSFXSR (see FXSR).

The legacy encodings on these pages write their result over the first operand, and most of those with a 128-bit memory operand require it to be aligned to 16 bytes. The VEX encodings of AVX, such as VADDPS, take a separate destination and no alignment requirement; mixing the two kinds costs time on many processors, which is why compilers insert VZEROUPPER. SSE and SSE2 are part of the x86-64 baseline.

Instructions

Mnemonics with at least one form in SSE. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
ADDPS	Adds four packed singles of the source to those of the destination XMM register.	2
ADDSS	Adds the low single of the source to the low single of the destination; the upper three elements are kept.	2
ANDNPS	Computes the bitwise AND of the inverted destination with the source, as packed singles.	2
ANDPS	Computes the bitwise AND of two XMM operands, as packed singles.	2
CMPPS	Compares four packed singles with one of eight predicates an immediate selects, into all-ones or all-zeros elements.	2
CMPSS	Compares the low singles with one of eight predicates an immediate selects, into an all-ones or all-zeros element.	2
COMISS	Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN raises an invalid exception.	2
CVTPI2PS	Converts two signed doublewords from an MMX register or memory to the low two singles of an XMM register.	2
CVTPS2PI	Converts the two low singles to signed doublewords in an MMX register, rounding as MXCSR says.	2
CVTSI2SS	Converts a signed 32- or 64-bit integer to single in the low element; the other elements of the destination are kept.	4
CVTSS2SI	Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR says.	4
CVTTPS2PI	Converts the two low singles to signed doublewords in an MMX register, truncating toward zero.	2
CVTTSS2SI	Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
DIVPS	Divides the four packed singles of the destination XMM register by those of the source.	2
DIVSS	Divides the low single of the destination by the low single of the source; the upper three elements are kept.	2
LDMXCSR	Loads the MXCSR register, the SSE control and status bits, from memory.	1
MASKMOVQ	Stores the bytes of an MMX register whose mask byte in a second MMX register has its top bit set to [RDI], non-temporally; SSE.	1
MAXPS	Returns the larger of each pair of packed singles, or the source element if either is NaN or both are zero.	2
MAXSS	Returns the larger of the low singles, or the source's if either is NaN or both are zero; the other elements are kept.	2
MINPS	Returns the smaller of each pair of packed singles, or the source element if either is NaN or both are zero.	2
MINSS	Returns the smaller of the low singles, or the source's if either is NaN or both are zero; the other elements are kept.	2
MOVAPS	Moves packed singles between XMM registers and memory, which must be aligned to 16 bytes.	4
MOVHLPS	Copies the high two singles of the source into the low half of the destination XMM register.	1
MOVHPS	Loads two singles from memory into the high half of an XMM register, or stores the high two to memory.	2
MOVLHPS	Copies the low two singles of the source into the high half of the destination XMM register.	1
MOVLPS	Loads two singles from memory into the low half of an XMM register, or stores the low two to memory.	2
MOVMSKPS	Copies the sign bits of four packed singles into the low bits of a general-purpose register.	1
MOVNTPS	Stores packed singles to 16-byte aligned memory with a non-temporal hint that avoids polluting the caches.	1
MOVNTQ	Stores an MMX register to memory with a non-temporal hint, which lets the write bypass the caches; SSE.	1
MOVSS	Moves the low single between XMM registers or to and from memory; a load zeroes the rest, a register move keeps it.	4
MOVUPS	Moves packed singles between XMM registers and memory without an alignment requirement.	4
MULPS	Multiplies the four packed singles of the destination XMM register by those of the source.	2
MULSS	Multiplies the low single of the destination by the low single of the source; the upper three elements are kept.	2
ORPS	Computes the bitwise OR of two XMM operands, as packed singles.	2
PAVGB	Computes the rounded averages of packed unsigned bytes of MMX or XMM registers.	2
PAVGW	Computes the rounded averages of packed unsigned words of MMX or XMM registers.	2
PEXTRW	Copies the word an immediate selects from an MMX or XMM register to a general-purpose register, or to memory (SSE4.1).	1
PINSRW	Inserts a word from a general-purpose register or memory into an MMX or XMM register at the position an immediate gives.	2
PMAXSW	Returns the larger of each pair of signed words of MMX or XMM registers.	2
PMAXUB	Returns the larger of each pair of unsigned bytes of MMX or XMM registers.	2
PMINSW	Returns the smaller of each pair of signed words of MMX or XMM registers.	2
PMINUB	Returns the smaller of each pair of unsigned bytes of MMX or XMM registers.	2
PMOVMSKB	Copies the top bit of each byte of an MMX or XMM register into the low bits of a general-purpose register.	1
PMULHUW	Multiplies packed unsigned words of MMX or XMM registers and keeps the high 16 bits of each product.	2
PREFETCHNTA	Hints that the cache line holding a byte of memory should be fetched close to the processor while polluting the caches little.	1
PREFETCHT0	Hints that the cache line holding a byte of memory should be fetched into all levels of the cache hierarchy.	1
PREFETCHT1	Hints that the cache line holding a byte of memory should be fetched into the second-level cache and higher.	1
PREFETCHT2	Hints that the cache line holding a byte of memory should be fetched into the third-level cache and higher.	1
PSADBW	Sums the absolute differences of unsigned bytes over each group of eight, into one 16-bit sum per quadword.	2
PSHUFW	Copies to an MMX register the words of another or of memory in the order four 2-bit fields of an immediate select; SSE.	2
RCPPS	Approximates the reciprocals of four packed singles, with a relative error of at most 1.5 times 2^-12.	2
RCPSS	Approximates the reciprocal of the low single, with a relative error of at most 1.5 times 2^-12; the other elements are kept.	2
RSQRTPS	Approximates the reciprocal square roots of four packed singles, with a relative error of at most 1.5 times 2^-12.	2
RSQRTSS	Approximates the reciprocal square root of the low single to within 1.5 times 2^-12; the other elements are kept.	2
SFENCE	Makes all earlier stores globally visible before any later store, which orders non-temporal and write-combining stores.	1
SHUFPS	Picks two singles from the destination for the low half and two from the source for the high half, as an immediate selects.	2
SQRTPS	Computes the square roots of four packed singles.	2
SQRTSS	Computes the square root of the low single of the source into the destination; the upper three elements are kept.	2
STMXCSR	Stores the MXCSR register, the SSE control and status bits, to memory.	1
SUBPS	Subtracts the four packed singles of the source from those of the destination XMM register.	2
SUBSS	Subtracts the low single of the source from the low single of the destination; the upper three elements are kept.	2
UCOMISS	Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception.	2
UNPCKHPS	Interleaves the high two singles of two XMM operands.	2
UNPCKLPS	Interleaves the low two singles of two XMM operands.	2
XORPS	Computes the bitwise XOR of two XMM operands, as packed singles; with the same register twice it zeroes it.	2

CPUID and processors

XED splits SSE into 3 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SSE. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSEMXCSR` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE_PREFETCH` SSE	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Instructions

CPUID and processors

Sources