SSE2 instruction set extension

SSE2 turned the XMM registers into general vector registers: two packed doubles (“PD” and “SD” forms) and integer vectors of bytes to quadwords, mostly the MMX instructions widened to 128 bits, which is why many pages here list both MMX and XMM forms. It also added LFENCE, MFENCE and MOVNTI.

Because every x86-64 processor has SSE2, the x86-64 ABIs pass and return float and double values in XMM registers and compilers do scalar floating point with SSE2 instead of the x87, which stays in use for long double (see the calling conventions).

Instructions

Mnemonics with at least one form in SSE2. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
ADDPD	Adds two packed doubles of the source to those of the destination XMM register.	2
ADDSD	Adds the low double of the source to the low double of the destination; the upper half of the destination is kept.	2
ANDNPD	Computes the bitwise AND of the inverted destination with the source, as packed doubles.	2
ANDPD	Computes the bitwise AND of two XMM operands, as packed doubles.	2
CMPPD	Compares two packed doubles with one of eight predicates an immediate selects, into all-ones or all-zeros elements.	2
CMPSD	Compares the low doubles with one of eight predicates an immediate selects, into an all-ones or all-zeros element.	2
COMISD	Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN raises an invalid exception.	2
CVTDQ2PD	Converts the two low signed doublewords of the source to doubles.	2
CVTDQ2PS	Converts four packed signed doublewords to singles, rounding as MXCSR says.	2
CVTPD2DQ	Converts two packed doubles to signed doublewords in the low half, rounding as MXCSR says and zeroing the high half.	2
CVTPD2PI	Converts two packed doubles to signed doublewords in an MMX register, rounding as MXCSR says.	2
CVTPD2PS	Converts two packed doubles to singles in the low half, rounding as MXCSR says and zeroing the high half.	2
CVTPI2PD	Converts two signed doublewords from an MMX register or memory to doubles.	2
CVTPS2DQ	Converts four packed singles to signed doublewords, rounding as MXCSR says.	2
CVTPS2PD	Converts the two low singles of the source to doubles, which is exact.	2
CVTSD2SI	Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR says.	4
CVTSD2SS	Converts the low double of the source to single, rounding as MXCSR says; the other elements of the destination are kept.	2
CVTSI2SD	Converts a signed 32- or 64-bit integer to double in the low element; the upper half of the destination is kept.	4
CVTSS2SD	Converts the low single of the source to double, which is exact; the upper half of the destination is kept.	2
CVTTPD2DQ	Converts two packed doubles to signed doublewords in the low half, truncating toward zero and zeroing the high half.	2
CVTTPD2PI	Converts two packed doubles to signed doublewords in an MMX register, truncating toward zero.	2
CVTTPS2DQ	Converts four packed singles to signed doublewords, truncating toward zero.	2
CVTTSD2SI	Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.	4
DIVPD	Divides the two packed doubles of the destination XMM register by those of the source.	2
DIVSD	Divides the low double of the destination by the low double of the source; the upper half is kept.	2
LFENCE	Waits until all earlier instructions have completed locally before any later one starts, which also bars speculative execution.	1
MASKMOVDQU	Stores the bytes of an XMM register whose mask byte in a second register has its top bit set to [RDI], non-temporally.	1
MAXPD	Returns the larger of each pair of packed doubles, or the source element if either is NaN or both are zero.	2
MAXSD	Returns the larger of the low doubles, or the source's if either is NaN or both are zero; the upper half is kept.	2
MFENCE	Makes all earlier loads and stores globally visible before any later load or store, a full memory barrier.	1
MINPD	Returns the smaller of each pair of packed doubles, or the source element if either is NaN or both are zero.	2
MINSD	Returns the smaller of the low doubles, or the source's if either is NaN or both are zero; the upper half is kept.	2
MOVAPD	Moves packed doubles between XMM registers and memory, which must be aligned to 16 bytes.	4
MOVD	Moves 32 bits between an MMX or XMM register and a general-purpose register or memory, zeroing the rest of a vector register.	4
MOVDQ2Q	Copies the low quadword of an XMM register to an MMX register.	1
MOVDQA	Moves 128 bits of integer data between XMM registers and memory, which must be aligned to 16 bytes.	4
MOVDQU	Moves 128 bits of integer data between XMM registers and memory without an alignment requirement.	4
MOVHPD	Loads a double from memory into the high half of an XMM register, or stores the high double to memory.	2
MOVLPD	Loads a double from memory into the low half of an XMM register, or stores the low double to memory.	2
MOVMSKPD	Copies the sign bits of two packed doubles into the low bits of a general-purpose register.	1
MOVNTDQ	Stores an XMM register to 16-byte aligned memory with a non-temporal hint that avoids polluting the caches.	1
MOVNTI	Stores a general-purpose register to memory with a non-temporal hint that avoids polluting the caches; SSE2.	2
MOVNTPD	Stores packed doubles to 16-byte aligned memory with a non-temporal hint that avoids polluting the caches.	1
MOVQ	Moves 64 bits between MMX or XMM registers, general-purpose registers and memory, zeroing the rest of an XMM destination.	8
MOVQ2DQ	Copies an MMX register to the low quadword of an XMM register and zeroes the high quadword.	1
MOVSD	Moves the low double between XMM registers or to and from memory; a load zeroes the upper half, a register move keeps it.	4
MOVUPD	Moves packed doubles between XMM registers and memory without an alignment requirement.	4
MULPD	Multiplies the two packed doubles of the destination XMM register by those of the source.	2
MULSD	Multiplies the low double of the destination by the low double of the source; the upper half is kept.	2
ORPD	Computes the bitwise OR of two XMM operands, as packed doubles.	2
PACKSSDW	Narrows signed doublewords of two MMX or XMM operands to words with signed saturation.	2
PACKSSWB	Narrows signed words of two MMX or XMM operands to bytes with signed saturation.	2
PACKUSWB	Narrows signed words of two MMX or XMM operands to bytes with unsigned saturation.	2
PADDB	Adds packed bytes of MMX or XMM registers, wrapping around on overflow.	2
PADDD	Adds packed doublewords of MMX or XMM registers, wrapping around on overflow.	2
PADDQ	Adds packed quadwords of MMX or XMM registers, wrapping around on overflow; SSE2.	4
PADDSB	Adds packed signed bytes of MMX or XMM registers with signed saturation.	2
PADDSW	Adds packed signed words of MMX or XMM registers with signed saturation.	2
PADDUSB	Adds packed unsigned bytes of MMX or XMM registers with unsigned saturation.	2
PADDUSW	Adds packed unsigned words of MMX or XMM registers with unsigned saturation.	2
PADDW	Adds packed words of MMX or XMM registers, wrapping around on overflow.	2
PAND	Computes the bitwise AND of two MMX or XMM operands.	2
PANDN	Computes the bitwise AND of the inverted destination with the source, in MMX or XMM registers.	2
PAVGB	Computes the rounded averages of packed unsigned bytes of MMX or XMM registers.	2
PAVGW	Computes the rounded averages of packed unsigned words of MMX or XMM registers.	2
PCMPEQB	Compares packed bytes of MMX or XMM registers for equality, into all-ones or all-zeros bytes.	2
PCMPEQD	Compares packed doublewords of MMX or XMM registers for equality, into all-ones or all-zeros elements.	2
PCMPEQW	Compares packed words of MMX or XMM registers for equality, into all-ones or all-zeros words.	2
PCMPGTB	Tests packed signed bytes of MMX or XMM registers for greater than, into all-ones or all-zeros bytes.	2
PCMPGTD	Tests packed signed doublewords of MMX or XMM registers for greater than, into all-ones or all-zeros elements.	2
PCMPGTW	Tests packed signed words of MMX or XMM registers for greater than, into all-ones or all-zeros words.	2
PEXTRW	Copies the word an immediate selects from an MMX or XMM register to a general-purpose register, or to memory (SSE4.1).	1
PINSRW	Inserts a word from a general-purpose register or memory into an MMX or XMM register at the position an immediate gives.	2
PMADDWD	Multiplies packed signed words of MMX or XMM registers and adds adjacent products into doublewords.	2
PMAXSW	Returns the larger of each pair of signed words of MMX or XMM registers.	2
PMAXUB	Returns the larger of each pair of unsigned bytes of MMX or XMM registers.	2
PMINSW	Returns the smaller of each pair of signed words of MMX or XMM registers.	2
PMINUB	Returns the smaller of each pair of unsigned bytes of MMX or XMM registers.	2
PMOVMSKB	Copies the top bit of each byte of an MMX or XMM register into the low bits of a general-purpose register.	1
PMULHUW	Multiplies packed unsigned words of MMX or XMM registers and keeps the high 16 bits of each product.	2
PMULHW	Multiplies packed signed words of MMX or XMM registers and keeps the high 16 bits of each product.	2
PMULLW	Multiplies packed words of MMX or XMM registers and keeps the low 16 bits of each product.	2
PMULUDQ	Multiplies the unsigned low doubleword of each quadword of MMX or XMM registers into 64-bit products; SSE2.	4
POR	Computes the bitwise OR of two MMX or XMM operands.	2
PSADBW	Sums the absolute differences of unsigned bytes over each group of eight, into one 16-bit sum per quadword.	2
PSHUFD	Rearranges the four doublewords of an XMM operand as an immediate selects.	2
PSHUFHW	Rearranges the upper four words of an XMM operand as an immediate selects, copying the lower four.	2
PSHUFLW	Rearranges the lower four words of an XMM operand as an immediate selects, copying the upper four.	2
PSLLD	Shifts packed doublewords of an MMX or XMM register left by a count from a register, memory or an immediate.	3
PSLLDQ	Shifts an XMM register left by the number of bytes an immediate gives, filling with zeros.	1
PSLLQ	Shifts packed quadwords of an MMX or XMM register left by a count from a register, memory or an immediate.	3
PSLLW	Shifts packed words of an MMX or XMM register left by a count from a register, memory or an immediate.	3
PSRAD	Shifts packed doublewords of an MMX or XMM register right arithmetically by a count from a register, memory or an immediate.	3
PSRAW	Shifts packed words of an MMX or XMM register right arithmetically by a count from a register, memory or an immediate.	3
PSRLD	Shifts packed doublewords of an MMX or XMM register right logically by a count from a register, memory or an immediate.	3
PSRLDQ	Shifts an XMM register right by the number of bytes an immediate gives, filling with zeros.	1
PSRLQ	Shifts packed quadwords of an MMX or XMM register right logically by a count from a register, memory or an immediate.	3
PSRLW	Shifts packed words of an MMX or XMM register right logically by a count from a register, memory or an immediate.	3
PSUBB	Subtracts packed bytes of MMX or XMM registers, wrapping around on overflow.	2
PSUBD	Subtracts packed doublewords of MMX or XMM registers, wrapping around on overflow.	2
PSUBQ	Subtracts packed quadwords of MMX or XMM registers, wrapping around on overflow; SSE2.	4
PSUBSB	Subtracts packed signed bytes of MMX or XMM registers with signed saturation.	2
PSUBSW	Subtracts packed signed words of MMX or XMM registers with signed saturation.	2
PSUBUSB	Subtracts packed unsigned bytes of MMX or XMM registers with unsigned saturation.	2
PSUBUSW	Subtracts packed unsigned words of MMX or XMM registers with unsigned saturation.	2
PSUBW	Subtracts packed words of MMX or XMM registers, wrapping around on overflow.	2
PUNPCKHBW	Interleaves the high bytes of two MMX or XMM operands.	2
PUNPCKHDQ	Interleaves the high doublewords of two MMX or XMM operands.	2
PUNPCKHQDQ	Interleaves the high quadwords of two XMM operands.	2
PUNPCKHWD	Interleaves the high words of two MMX or XMM operands.	2
PUNPCKLBW	Interleaves the low bytes of two MMX or XMM operands.	2
PUNPCKLDQ	Interleaves the low doublewords of two MMX or XMM operands.	2
PUNPCKLQDQ	Interleaves the low quadwords of two XMM operands.	2
PUNPCKLWD	Interleaves the low words of two MMX or XMM operands.	2
PXOR	Computes the bitwise XOR of two MMX or XMM operands; with the same register twice it zeroes it.	2
SHUFPD	Picks one double from each operand for the two result positions, as an immediate selects.	2
SQRTPD	Computes the square roots of two packed doubles.	2
SQRTSD	Computes the square root of the low double of the source into the low double of the destination; the upper half is kept.	2
SUBPD	Subtracts the two packed doubles of the source from those of the destination XMM register.	2
SUBSD	Subtracts the low double of the source from the low double of the destination; the upper half is kept.	2
UCOMISD	Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception.	2
UNPCKHPD	Interleaves the high doubles of two XMM operands.	2
UNPCKLPD	Interleaves the low doubles of two XMM operands.	2
XORPD	Computes the bitwise XOR of two XMM operands, as packed doubles; with the same register twice it zeroes it.	2

CPUID and processors

XED splits SSE2 into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SSE2. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2MMX` SSE2	SSE2 + MMX `CPUID.01H:EDX[26]` SSE2 `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Instructions

CPUID and processors

Sources