x86-64.net

Vector (SSE, AVX and AVX10)

SSE3

SSE3 adds horizontal additions and subtractions, the ADDSUB instructions for complex arithmetic, duplicating moves, LDDQU and the truncating x87 store FISTTP.

CPUID
SSE3
CPUID.01H:ECX[0]
Instructions
11 mnemonics
Processors
Every x86-64 processor in XED’s model and Zen 3 to Zen 6
Linux flag
pni

SSE3 is a small set: horizontal additions and subtractions within one register (HADDPS and relatives), the alternating ADDSUBPS and ADDSUBPD that complex multiplication needs, duplicating loads such as MOVDDUP, the unaligned load LDDQU, and FISTTP, which converts an x87 value to an integer with truncation, as C requires, without changing the rounding mode. MONITOR and MWAIT came at the same time but have a CPUID bit of their own. SSE3 is part of x86-64-v2; Linux shows it as pni.

Instructions

Mnemonics with at least one form in SSE3. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
ADDSUBPDSubtracts in the low double and adds in the high double, the step of complex multiplication; SSE3.2
ADDSUBPSSubtracts in the even-numbered singles and adds in the odd-numbered ones, the step of complex multiplication; SSE3.2
FISTTPStores ST0 as a signed 16-, 32- or 64-bit integer, truncating toward zero whatever the rounding mode, and pops it; SSE3.3
HADDPDAdds the two doubles within each source, the destination's sum going low and the source's high; SSE3.2
HADDPSAdds adjacent pairs of singles within each source, the destination's two sums going low and the source's high; SSE3.2
HSUBPDSubtracts the high double from the low one within each source, the destination's result going low; SSE3.2
HSUBPSSubtracts the odd single from the even one in adjacent pairs of each source, the destination's results going low; SSE3.2
LDDQULoads 128 unaligned bits into an XMM register like MOVDQU, but may read more bytes around them, for loads across cache lines; SSE3.1
MOVDDUPLoads or copies a double and duplicates it into both halves of an XMM register; SSE3.2
MOVSHDUPDuplicates each odd-numbered single into the even position below it; SSE3.2
MOVSLDUPDuplicates each even-numbered single into the odd position above it; SSE3.2

CPUID and processors

XED splits SSE3 into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SSE3. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE3

SSE3
CPUID.01H:ECX[0] SSE3

Every x86-64 processor in XED’s model and Zen 3 to Zen 6
SSE3X87

SSE3
CPUID.01H:ECX[0] SSE3

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.