SSE4.1 instruction set extension

SSE4.1 filled gaps in the vector instruction set: blends by an immediate or by a mask in XMM0 (BLENDVPS, PBLENDVB), rounding to integers (ROUNDPS), dot products, sign and zero extension of packed integers (PMOVZXBW and relatives), 32-bit multiplies (PMULLD), minimum and maximum of more integer types, inserting and extracting elements, the test PTEST and the streaming load MOVNTDQA. It is part of x86-64-v2.

Instructions

Mnemonics with at least one form in SSE4.1. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
BLENDPD	Picks each double from the destination or the source, as a bit of an immediate says; SSE4.1.	2
BLENDPS	Picks each single from the destination or the source, as a bit of an immediate says; SSE4.1.	2
BLENDVPD	Picks each double from the destination or the source by the sign bit of the matching element of XMM0; SSE4.1.	2
BLENDVPS	Picks each single from the destination or the source by the sign bit of the matching element of XMM0; SSE4.1.	2
DPPD	Computes a dot product of the packed doubles, with an immediate choosing which products to add and where the sum goes.	2
DPPS	Computes a dot product of the packed singles, with an immediate choosing which products to add and where the sum goes.	2
EXTRACTPS	Copies the single that an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1.	2
INSERTPS	Inserts a single from a register or memory into an XMM register at the position an immediate gives, and can zero other elements.	2
MOVNTDQA	Loads 16 aligned bytes with a non-temporal hint, which lets it read write-combining memory efficiently; SSE4.1.	1
MPSADBW	Computes eight word sums of absolute differences between a 4-byte block of the source and sliding blocks of the destination.	2
PACKUSDW	Narrows signed doublewords of two XMM operands to words with unsigned saturation; SSE4.1.	2
PBLENDVB	Picks each byte from the destination or the source by the top bit of the matching byte of XMM0; SSE4.1.	2
PBLENDW	Picks each word from the destination or the source, as a bit of an immediate says; SSE4.1.	2
PCMPEQQ	Compares packed quadwords for equality, into all-ones or all-zeros quadwords; SSE4.1.	2
PEXTRB	Copies the byte an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1.	2
PEXTRD	Copies the doubleword an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1.	2
PEXTRQ	Copies the quadword an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1.	2
PEXTRW	Copies the word an immediate selects from an MMX or XMM register to a general-purpose register, or to memory (SSE4.1).	2
PHMINPOSUW	Finds the smallest unsigned word of an XMM operand and returns it with its index in the low two words; SSE4.1.	2
PINSRB	Inserts a byte from a general-purpose register or memory into an XMM register at the position an immediate gives; SSE4.1.	2
PINSRD	Inserts a doubleword from a general-purpose register or memory into an XMM register where an immediate says; SSE4.1.	2
PINSRQ	Inserts a quadword from a general-purpose register or memory into an XMM register where an immediate says; SSE4.1.	2
PMAXSB	Returns the larger of each pair of signed bytes; SSE4.1.	2
PMAXSD	Returns the larger of each pair of signed doublewords; SSE4.1.	2
PMAXUD	Returns the larger of each pair of unsigned doublewords; SSE4.1.	2
PMAXUW	Returns the larger of each pair of unsigned words; SSE4.1.	2
PMINSB	Returns the smaller of each pair of signed bytes; SSE4.1.	2
PMINSD	Returns the smaller of each pair of signed doublewords; SSE4.1.	2
PMINUD	Returns the smaller of each pair of unsigned doublewords; SSE4.1.	2
PMINUW	Returns the smaller of each pair of unsigned words; SSE4.1.	2
PMOVSXBD	Sign-extends the four low bytes of the source to doublewords; SSE4.1.	2
PMOVSXBQ	Sign-extends the two low bytes of the source to quadwords; SSE4.1.	2
PMOVSXBW	Sign-extends the eight low bytes of the source to words; SSE4.1.	2
PMOVSXDQ	Sign-extends the two low doublewords of the source to quadwords; SSE4.1.	2
PMOVSXWD	Sign-extends the four low words of the source to doublewords; SSE4.1.	2
PMOVSXWQ	Sign-extends the two low words of the source to quadwords; SSE4.1.	2
PMOVZXBD	Zero-extends the four low bytes of the source to doublewords; SSE4.1.	2
PMOVZXBQ	Zero-extends the two low bytes of the source to quadwords; SSE4.1.	2
PMOVZXBW	Zero-extends the eight low bytes of the source to words; SSE4.1.	2
PMOVZXDQ	Zero-extends the two low doublewords of the source to quadwords; SSE4.1.	2
PMOVZXWD	Zero-extends the four low words of the source to doublewords; SSE4.1.	2
PMOVZXWQ	Zero-extends the two low words of the source to quadwords; SSE4.1.	2
PMULDQ	Multiplies the signed low doubleword of each quadword into 64-bit products; SSE4.1.	2
PMULLD	Multiplies packed doublewords and keeps the low 32 bits of each product; SSE4.1.	2
PTEST	Sets ZF if the AND of two XMM operands is all zeros and CF if the AND of the inverted destination with the source is; SSE4.1.	2
ROUNDPD	Rounds two packed doubles to integral values with the rounding mode of an immediate or MXCSR; SSE4.1.	2
ROUNDPS	Rounds four packed singles to integral values with the rounding mode of an immediate or MXCSR; SSE4.1.	2
ROUNDSD	Rounds the low double of the source to an integral value, by an immediate or MXCSR; the upper half is kept.	2
ROUNDSS	Rounds the low single of the source to an integral value, by an immediate or MXCSR; the other elements are kept.	2

CPUID and processors

XED splits SSE4.1 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SSE4.1. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

Instructions

CPUID and processors

Sources