x86-64.net

Vector (SSE, AVX and AVX10)

SSE4.2

SSE4.2 adds the string and text compares PCMPESTRI to PCMPISTRM, a 64-bit signed compare and the CRC32 instruction; POPCNT, often counted with it, has a CPUID bit of its own.

CPUID
SSE4.2
CPUID.01H:ECX[20]
Instructions
6 mnemonics
Processors
Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
Linux flag
sse4_2

SSE4.2 added four string instructions, PCMPESTRI, PCMPESTRM, PCMPISTRI and PCMPISTRM, which compare up to 16 bytes or eight words of two strings in one of several modes that an immediate selects, such as equal-any or ranges, for searching and parsing text. It also added PCMPGTQ and CRC32, which computes the CRC-32C checksum of a byte, word, doubleword or quadword. POPCNT came with it on Intel’s processors but has a CPUID bit of its own. SSE4.2 is part of x86-64-v2.

Instructions

Mnemonics with at least one form in SSE4.2. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CRC32Accumulates a CRC-32C checksum (Castagnoli polynomial) over a 1-, 2-, 4- or 8-byte operand.4
PCMPESTRICompares two strings of explicit lengths in EAX and EDX (RAX and RDX with REX.W) as an immediate says, returning an index in ECX.4
PCMPESTRMCompares two strings of explicit lengths in EAX and EDX (RAX and RDX with REX.W) as an immediate says, returning a mask in XMM0.4
PCMPGTQTests packed signed quadwords for greater than, into all-ones or all-zeros quadwords; SSE4.2.2
PCMPISTRICompares two zero-terminated strings in XMM registers as an immediate says, returning an index in ECX; SSE4.2.4
PCMPISTRMCompares two zero-terminated strings in XMM registers as an immediate says, returning a bit or byte mask in XMM0.2

CPUID and processors

XED splits SSE4.2 into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SSE4.2. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE42

SSE4.2
CPUID.01H:ECX[20] SSE4.2

Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.