CPUID
SSE4A
CPUID.80000001H:ECX[6]
Instructions
4 mnemonics
Processors
K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Bobcat, Dhyana, Excavator, Jaguar, Puma, Steamroller, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 (from the CPU data, which follows GCC)
Linux flag
sse4a

Instructions

Mnemonics with at least one form in SSE4a. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
EXTRQExtracts a bit field, whose length and position an immediate or a register gives, from the low quadword of an XMM register; SSE4a.2
INSERTQInserts the low bits of one XMM register as a bit field into the low quadword of another; SSE4a.2
MOVNTSDStores the low double of an XMM register to memory with a non-temporal hint; SSE4a.1
MOVNTSSStores the low single of an XMM register to memory with a non-temporal hint; SSE4a.1

CPUID and processors

XED splits SSE4a into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SSE4a. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE4a

SSE4A
CPUID.80000001H:ECX[6] SSE4A

K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit, 256-Bit, and 512-Bit Media Instructions (26568, rev. 3.27, July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.