Vector (SSE, AVX and AVX10)
SSSE3
Supplemental SSE3 adds byte shuffles with PSHUFB, byte alignment with PALIGNR, horizontal integer additions, absolute values, sign changes and two fixed-point multiplies.
- CPUID
- SSSE3
CPUID.01H:ECX[9] - Instructions
- 16 mnemonics
- Processors
- Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Bonnell, Saltwell, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
- Linux flag
ssse3
Supplemental SSE3 added integer instructions for MMX and XMM registers, among them some of the most used shuffles: PSHUFB, which picks each byte of the result by an index, and PALIGNR, which extracts bytes across two registers. The rest are horizontal integer additions and subtractions, absolute values, PSIGNB and its relatives, and the multiplies PMADDUBSW and PMULHRSW. It is part of x86-64-v2.
Instructions
| Mnemonic | Summary | Forms |
|---|---|---|
| PABSB | Computes the absolute values of packed signed bytes of an MMX or XMM operand; SSSE3. | 4 |
| PABSD | Computes the absolute values of packed signed doublewords of an MMX or XMM operand; SSSE3. | 4 |
| PABSW | Computes the absolute values of packed signed words of an MMX or XMM operand; SSSE3. | 4 |
| PALIGNR | Concatenates two MMX or XMM operands and extracts a register's worth of bytes at the byte offset an immediate gives; SSSE3. | 4 |
| PHADDD | Adds adjacent pairs of doublewords within each MMX or XMM operand, the destination's sums going low; SSSE3. | 4 |
| PHADDSW | Adds adjacent pairs of signed words within each operand with signed saturation, the destination's sums going low; SSSE3. | 4 |
| PHADDW | Adds adjacent pairs of words within each MMX or XMM operand, the destination's sums going low; SSSE3. | 4 |
| PHSUBD | Subtracts the odd doubleword from the even one in adjacent pairs of each MMX or XMM operand; SSSE3. | 4 |
| PHSUBSW | Subtracts the odd signed word from the even one in adjacent pairs of each operand with signed saturation; SSSE3. | 4 |
| PHSUBW | Subtracts the odd word from the even one in adjacent pairs of each MMX or XMM operand; SSSE3. | 4 |
| PMADDUBSW | Multiplies unsigned bytes of the destination by signed bytes of the source and adds adjacent products with signed saturation. | 4 |
| PMULHRSW | Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result; SSSE3. | 4 |
| PSHUFB | Rearranges the bytes of an MMX or XMM register by an index byte per result, which zeroes the byte when its top bit is set; SSSE3. | 4 |
| PSIGNB | Negates, zeroes or keeps each signed byte of the destination as the matching source byte is negative, zero or positive; SSSE3. | 4 |
| PSIGND | Negates, zeroes or keeps each doubleword of the destination as the matching source element is negative, zero or positive. | 4 |
| PSIGNW | Negates, zeroes or keeps each signed word of the destination as the matching source word is negative, zero or positive; SSSE3. | 4 |
CPUID and processors
XED splits SSSE3 into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.