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System

SVM (AMD-V) virtualization instructions

SVM, AMD's virtualization extension (AMD-V), runs a guest with VMRUN from a control block in memory, the VMCB, until an intercepted event returns control to the hypervisor.

AMD's virtualization extension: Intel processors implement VMX instead.

CPUID
SVM
CPUID.80000001H:ECX[2]
Instructions
8 mnemonics
Processors
K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

SVM (Secure Virtual Machine), sold as AMD-V, is AMD’s counterpart of Intel’s VMX; the two have nothing in common at the instruction level. The hypervisor describes each guest in a virtual machine control block (VMCB) in memory and enters it with VMRUN, which returns when an event that the VMCB intercepts occurs; VMLOAD and VMSAVE move the state that VMRUN leaves alone. A guest calls its hypervisor with VMMCALL, the counterpart of VMX’s VMCALL. CLGI and STGI hold interrupts off around the switch, and SKINIT starts a measured, trusted loader, as Intel’s GETSEC[SENTER] does. The encrypted guests of SEV-SNP build on SVM; see SEV-SNP.

Instructions

Mnemonics with at least one form in SVM. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CLGIClears the global interrupt flag (GIF), which holds off all external interrupts; AMD SVM.1
INVLPGAInvalidates the TLB entry of the page at the address in rAX for the address space ID in ECX; AMD SVM.1
SKINITReinitializes the processor securely and starts the secure loader at the physical address in EAX after measuring it; AMD SVM.1
STGISets the global interrupt flag (GIF) again, letting external interrupts through; AMD SVM.1
VMLOADLoads the processor state that VMRUN does not load (segment and system registers) from the VMCB at the address in rAX; AMD SVM.1
VMMCALLExits from a guest to its hypervisor with a VM exit, for a call whose meaning the hypervisor defines; AMD SVM.1
VMRUNRuns the guest that the virtual machine control block (VMCB) at the physical address in rAX describes; AMD SVM.1
VMSAVESaves the processor state that VMRUN does not save to the VMCB at the physical address in rAX; AMD SVM.1

CPUID and processors

XED splits SVM into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SVM. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SVM

SVM
CPUID.80000001H:ECX[2] SVM

K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF
  4. AMD64 Architecture Programmer's Manual, Volume 2: System Programming (24593, rev. 3.42, March 2024), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.