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System

SYSCALL/SYSRET

SYSCALL and SYSRET, the fast system call and return of 64-bit mode, which change privilege level with an entry point and segments held in MSRs instead of a gate in the IDT.

CPUID
See the ISA sets below.
Instructions
2 mnemonics
Processors
Every x86-64 processor in XED’s model and Zen 3 to Zen 6
Linux flag
syscall

SYSCALL is how 64-bit code enters the operating system, and SYSRET how the kernel returns. They avoid the descriptor lookups of an interrupt gate: the kernel’s entry point is in the IA32_LSTAR MSR, its code and stack segments follow from IA32_STAR, and IA32_FMASK says which flags SYSCALL clears. SYSCALL keeps the return address in RCX and the flags in R11 and does not switch stacks, which the kernel does first; the system call conventions avoid RCX and R11 for arguments for that reason.

The kernel enables them with the SCE bit of IA32_EFER. CPUID leaf 80000001H, bit 11 of EDX, reports them; Intel processors support SYSCALL and SYSRET only in 64-bit mode and set that bit only there, while AMD’s also run them in 32-bit mode, which XED lists as separate forms. With FRED enabled, SYSCALL delivers an event instead and SYSRET cannot be used; the kernel returns with ERETU.

Instructions

Mnemonics with at least one form in SYSCALL/SYSRET. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
SYSCALLEnters the kernel fast: saves RIP in RCX and RFLAGS in R11 and jumps to IA32_LSTAR at ring 0; the system call of 64-bit Linux.2
SYSRETReturns from SYSCALL to user mode, loading RIP from RCX and RFLAGS from R11; with REX.W to 64-bit code, without to 32-bit code.3

CPUID and processors

XED splits SYSCALL/SYSRET into 2 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SYSCALL/SYSRET. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AMD

No CPUID bit: part of the base instruction set.

K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.