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System

SYSENTER/SYSEXIT

SYSENTER and SYSEXIT, a fast system call and return that take the kernel's entry point and stack from MSRs, which 32-bit code uses on Intel processors.

CPUID
SEP
CPUID.01H:EDX[11]
Instructions
2 mnemonics
Processors
Every x86-64 processor in XED’s model and Zen 3 to Zen 6

SYSENTER and SYSEXIT came with the Pentium II as a fast way into and out of the kernel. SYSENTER takes the kernel’s code segment, entry point and stack pointer from three MSRs, IA32_SYSENTER_CS, IA32_SYSENTER_EIP and IA32_SYSENTER_ESP, and saves nothing about the caller. User code must keep its own return address and stack pointer where the kernel finds them, and SYSEXIT returns to the address in RDX (or EDX) with the stack pointer in RCX. They are not a call and return pair.

That is why 32-bit Linux does not execute SYSENTER in programs itself: the C library calls a function of the kernel’s vDSO, which uses SYSENTER where the processor has it (see the system call conventions). 64-bit code uses SYSCALL. The CPUID bit is called SEP; Intel’s manual warns that early Pentium Pro models report it without having the instructions.

Instructions

Mnemonics with at least one form in SYSENTER/SYSEXIT. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
SYSENTEREnters the kernel at the address and stack in the SYSENTER MSRs at ring 0, without saving a return point; used by 32-bit systems.1
SYSEXITReturns from a SYSENTER entry to ring 3 at the address in RDX or EDX, with the stack pointer in RCX or ECX; ring 0 only.1

CPUID and processors

XED splits SYSENTER/SYSEXIT into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of SYSENTER/SYSEXIT. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SEP

SEP
CPUID.01H:EDX[11] SEP

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.