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General-purpose

TBM (Trailing Bit Manipulation, AMD)

Trailing Bit Manipulation (TBM) computes masks and fills around the lowest set or clear bit of a register in one instruction, and adds BEXTR with an immediate.

An AMD extension: Intel processors do not have this instruction.

CPUID
TBM
CPUID.80000001H:ECX[21]
Instructions
10 mnemonics
Processors
Piledriver, Excavator, Steamroller (from the CPU data, which follows GCC)
Linux flag
tbm

Instructions

Mnemonics with at least one form in TBM. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
BEXTRExtracts a bit field whose start and length come from a second register; APX adds a form that leaves the flags unchanged.4
BLCFILLClears the bits below the lowest clear bit of a general-purpose register or memory (x & (x + 1)); TBM.4
BLCISets every bit but the lowest clear bit of the source (x | ~(x + 1)); TBM.4
BLCICIsolates the lowest clear bit of the source as the only set bit (~x & (x + 1)); TBM.4
BLCMSKMakes a mask of the lowest clear bit of the source and the bits below it (x ^ (x + 1)); TBM.4
BLCSSets the lowest clear bit of the source (x | (x + 1)); TBM.4
BLSFILLSets the bits below the lowest set bit of the source (x | (x - 1)); TBM.4
BLSICClears the lowest set bit of the source and sets every other bit (~x | (x - 1)); TBM.4
T1MSKCMakes a mask of the trailing ones of the source, inverted (~x | (x + 1)); TBM.4
TZMSKMakes a mask of the trailing zeros of the source (~x & (x - 1)); TBM.4

CPUID and processors

XED splits TBM into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of TBM. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
TBM

TBM
CPUID.80000001H:ECX[21] TBM

Piledriver, Zen, Zen+, Zen 2

Note: XED's Zen chips inherit TBM from its Piledriver chip; GCC's -march=znver1 and later do not enable TBM.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.38, July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.