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Memory, caches and atomics

TSXLDTRK

Suspend load address tracking: within an RTM transaction, XSUSLDTRK and XRESLDTRK bracket loads that stay out of the read set, so they cannot cause conflicts.

CPUID
TSX_LDTRK
CPUID.(EAX=07H,ECX=0):EDX[16]
Instructions
2 mnemonics
Processors
Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

An RTM transaction tracks the addresses it reads, and a store to any of them by another core aborts it. Some reads, such as those of data the transaction only looks at in passing, need not cause aborts. XSUSLDTRK suspends the tracking of loads inside a transaction and XRESLDTRK resumes it; loads in between do not join the read set. Stores are still tracked. Outside a transaction both are NOPs.

Instructions

Mnemonics with at least one form in TSXLDTRK. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
XRESLDTRKEnds a TSXLDTRK region of an RTM transaction, so that later loads join the transaction's read set again.1
XSUSLDTRKStarts a region of an RTM transaction whose loads stay out of its read set, so they cannot cause conflicts.1

CPUID and processors

XED splits TSXLDTRK into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of TSXLDTRK. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
TSX_LDTRK

TSX_LDTRK
CPUID.(EAX=07H,ECX=0):EDX[16] TSX_LDTRK

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.