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System

UINTR

User interrupts: a thread can send an interrupt with SENDUIPI to a thread on another core, whose handler then runs in user mode without the kernel.

CPUID
UINTR
CPUID.(EAX=07H,ECX=0):EDX[5]
Instructions
5 mnemonics
Processors
Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest

User interrupts let one thread interrupt another without the kernel on the path. The sender executes SENDUIPI with an index into its user-interrupt target table, set up by the operating system, which names the receiving thread and a vector. If that thread is running, the processor delivers the interrupt to it directly: it pushes the return address, flags and stack pointer and jumps to the thread’s user-mode handler, which returns with UIRET. The receiver can hold user interrupts back with CLUI, allow them with STUI, and read the user interrupt flag with TESTUI. All of them work only in 64-bit mode.

Instructions

Mnemonics with at least one form in UINTR. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
CLUIClears the user interrupt flag (UIF), holding user interrupts back from the next instruction on.1
SENDUIPISends a user interprocessor interrupt through the entry of the user-interrupt target table that a register selects.1
STUISets the user interrupt flag (UIF), so that pending user interrupts can be delivered right after it.1
TESTUICopies the user interrupt flag (UIF) into CF.1
UIRETReturns from a user-interrupt handler, popping the RIP, RFLAGS and RSP that delivery pushed, and sets UIF again.1

CPUID and processors

XED splits UINTR into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of UINTR. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
UINTR

UINTR
CPUID.(EAX=07H,ECX=0):EDX[5] UINTR

Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.