System
USER_MSR
Lets user-mode code read and write the model-specific registers that the operating system allows in a bitmap.
- CPUID
- USER_MSR
CPUID.(EAX=07H,ECX=1):EDX[15] - Instructions
- 2 mnemonics
- Processors
- Clearwater Forest
URDMSR and UWRMSR let user-mode code read and write model-specific registers that the operating system has chosen to expose. The kernel enables them and points the IA32_USER_MSR_CTL MSR at a 4-KiB bitmap: its low half has one bit per MSR address from 0 to 3FFFH for URDMSR, its high half the same for UWRMSR, and any access without its bit set raises #GP. The SDM currently names IA32_UARCH_MISC_CTL as the only MSR UWRMSR may write. Both instructions exist only in 64-bit mode, with the address in a register or an immediate. Intel lists Clearwater Forest as the first processor with them.
Instructions
CPUID and processors
XED splits USER_MSR into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.
| ISA set | CPUID | Processors in XED |
|---|---|---|
USER_MSR | USER_MSR | Clearwater Forest |
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.