x86-64.net

Cryptography

VAES

VAES extends the AES round instructions to 256-bit YMM registers, one block per 128-bit lane; with AVX-512 or AVX10 they reach 512 bits.

CPUID
VAES
CPUID.(EAX=07H,ECX=0):ECX[9]
Instructions
4 mnemonics
Processors
Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 3, Zen 4, Zen 5, Zen 6
Linux flag
vaes

VAES gives the AES round instructions VAESENC, VAESENCLAST, VAESDEC and VAESDECLAST forms for 256-bit YMM registers, which process one AES block in each 128-bit lane with the round key of the same lane. With AVX-512 or AVX10 they also take ZMM registers, four blocks at a time. The 128-bit VEX forms belong to AES-NI with AVX.

Instructions

Mnemonics with at least one form in VAES. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VAESDECPerforms one round of AES decryption on each 128-bit lane with the round key of the matching lane.2
VAESDECLASTPerforms the last round of AES decryption on each 128-bit lane with the round key of the matching lane.2
VAESENCPerforms one round of AES encryption on each 128-bit lane with the round key of the matching lane.2
VAESENCLASTPerforms the last round of AES encryption on each 128-bit lane with the round key of the matching lane.2

CPUID and processors

XED splits VAES into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of VAES. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
VAES

VAES
CPUID.(EAX=07H,ECX=0):ECX[9] VAES

Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.