CPUID
See the ISA sets below.
Instructions
9 mnemonics
Processors
None in XED’s chip model.

VIA built PadLock units into its processors: a random number generator that XSTORE reads, the Advanced Cryptography Engine for AES (XCRYPTECB, XCRYPTCBC and the other modes), a hash engine for SHA-1 and SHA-256 (XSHA1, XSHA256) and a Montgomery multiplier (MONTMUL). Each instruction takes pointers and counts in general-purpose registers and works through a whole buffer; all but XSTORE are written with a REP prefix. CPUID function C000_0001h reports each unit twice, as present and as enabled.

The Linux kernel’s drivers use these instructions on VIA processors from the C3 to the Nano. On Zhaoxin’s processors the kernel turns the AES unit on where it is present but disabled, while its SHA driver leaves them out (family 7 and later) because its self-tests fail there. XED’s chip model knows PadLock only on a VIA chip without 64-bit mode, so the processor lists on these pages are empty.

Instructions

Mnemonics with at least one form in VIA PadLock. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
MONTMULPerforms a Montgomery multiplication in the PadLock Montgomery Multiplier, on operands that a block at [ESI] describes; VIA PadLock.1
XCRYPTCBCEncrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in CBC mode; rAX, rBX and rDX point to IV, key and control word; VIA PadLock.1
XCRYPTCFBEncrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in CFB mode; rAX, rBX and rDX point to IV, key and control word; VIA PadLock.1
XCRYPTCTREncrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in counter mode; rAX, rBX and rDX point to counter, key and control word.1
XCRYPTECBEncrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in ECB mode, the key at [rBX] and a control word at [rDX]; VIA PadLock.1
XCRYPTOFBEncrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in OFB mode; rAX, rBX and rDX point to IV, key and control word; VIA PadLock.1
XSHA1Hashes the data at [rSI] with SHA-1 into the state at [rDI]; rCX gives the total length and rAX the bytes already hashed; VIA PadLock.1
XSHA256Hashes the data at [rSI] with SHA-256 into the state at [rDI]; rCX gives the total length and rAX the bytes already hashed; VIA PadLock.1
XSTOREStores random bytes from the processor's random number generator at [rDI], at the rate EDX selects, and returns their count in EAX; VIA PadLock.2

CPUID and processors

XED splits VIA PadLock into 4 ISA sets. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of VIA PadLock. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
VIA_PADLOCK_AES

VIA_PADLOCK_AES + VIA_PADLOCK_AES_EN
CPUID.C0000001H:EDX[6] VIA_PADLOCK_AES
CPUID.C0000001H:EDX[7] VIA_PADLOCK_AES_EN

None in XED’s model.
VIA_PADLOCK_MONTMUL

VIA_PADLOCK_PMM + VIA_PADLOCK_PMM_EN
CPUID.C0000001H:EDX[12] VIA_PADLOCK_PMM
CPUID.C0000001H:EDX[13] VIA_PADLOCK_PMM_EN

None in XED’s model.
VIA_PADLOCK_RNG

VIA_PADLOCK_RNG + VIA_PADLOCK_RNG_EN
CPUID.C0000001H:EDX[2] VIA_PADLOCK_RNG
CPUID.C0000001H:EDX[3] VIA_PADLOCK_RNG_EN

None in XED’s model.
VIA_PADLOCK_SHA

VIA_PADLOCK_SHA + VIA_PADLOCK_SHA_EN
CPUID.C0000001H:EDX[10] VIA_PADLOCK_SHA
CPUID.C0000001H:EDX[11] VIA_PADLOCK_SHA_EN

None in XED’s model.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Linux 7.3: drivers/crypto/padlock-aes.c and padlock-sha.c (VIA PadLock AES and SHA)
  3. Linux 7.3: drivers/char/hw_random/via-rng.c (VIA PadLock random number generator)
  4. Linux 7.3: arch/x86/kernel/cpu/zhaoxin.c (enables PadLock ACE on Zhaoxin processors)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.