x86-64.net

Cryptography

VPCLMULQDQ

VPCLMULQDQ performs one carry-less multiplication per 128-bit lane of a YMM register, and of a ZMM register with AVX-512 or AVX10.

CPUID
VPCLMULQDQ
CPUID.(EAX=07H,ECX=0):ECX[10]
Instructions
1 mnemonic
Processors
Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 3, Zen 4, Zen 5, Zen 6
Linux flag
vpclmulqdq

VPCLMULQDQ performs the carry-less multiplication of PCLMULQDQ in every 128-bit lane of a YMM register, and of a ZMM register with AVX-512 or AVX10, with the same immediate choosing the quadwords in every lane. The 128-bit VEX form needs only PCLMULQDQ and AVX.

Instructions

Mnemonics with at least one form in VPCLMULQDQ. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
VPCLMULQDQCarry-less multiplies one quadword of each source, chosen by an immediate, into a 128-bit product in each 128-bit lane.2

CPUID and processors

XED splits VPCLMULQDQ into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of VPCLMULQDQ. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
VPCLMULQDQ

VPCLMULQDQ
CPUID.(EAX=07H,ECX=0):ECX[10] VPCLMULQDQ

Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.