CPUID
WBNOINVD
CPUID.80000008H:EBX[9]
Instructions
1 mnemonic
Processors
Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

WBINVD writes every modified line of the caches back to memory and then invalidates all of them, so the next accesses miss. WBNOINVD does the write-back but keeps the lines valid, for when software needs memory up to date without losing the cache contents. Its encoding is WBINVD with an F3 prefix, which older processors ignore and execute as WBINVD. Both run only at privilege level 0.

Instructions

Mnemonics with at least one form in WBNOINVD. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
WBNOINVDWrites every modified line of the caches back to memory but keeps the lines cached; ring 0 only.1

CPUID and processors

XED splits WBNOINVD into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of WBNOINVD. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.