XSAVE instruction set extension

Every extension that adds registers adds state that an operating system must save on a context switch. The XSAVE feature set handles all of it with one mechanism: the state is divided into numbered components, and a 64-bit bitmap selects which ones an instruction saves or restores. Intel’s manual defines components 0 to 18:

XSAVE state components.

Components	State
0, 1	x87 and SSE (XMM registers, MXCSR)
2	AVX: the upper halves of YMM0 to YMM15
3, 4	MPX bound registers and configuration
5 to 7	AVX-512: mask registers, upper halves of ZMM0 to ZMM15, ZMM16 to ZMM31
9	PKRU, the protection-key rights
17, 18	AMX: tile configuration and 8 KB of tile data
8, 10 to 16	Supervisor state, such as Processor Trace and CET

APX adds component 19 for R16 to R31.

The operating system enables user components in XCR0 with XSETBV and sets CR4.OSXSAVE, which CPUID reports back as OSXSAVE; programs read XCR0 with XGETBV before they use AVX, so that registers the kernel does not save are never touched. XSAVE and XRSTOR save and restore the components that both XCR0 and EDX:EAX select. Supervisor components need XSAVES; XSAVEOPT and XSAVEC save less.

The size of the area depends on the processor and on XCR0, so CPUID leaf 0DH reports it. On Linux the signal frame contains an XSAVE area too, which is why AMX’s tile data is enabled per process on request: see how the ABIs treat vector state.

Instructions

Mnemonics with at least one form in XSAVE. Each page lists all forms of the mnemonic, including those of other extensions.

Mnemonic	Summary	Forms
XGETBV	Reads the extended control register that ECX selects into EDX:EAX; XCR0 says which state components the OS lets XSAVE manage.	1
XRSTOR	Restores the state components that XCR0 and EDX:EAX select from an XSAVE area, setting those the area marks unused to their initial state.	2
XSAVE	Saves the state components that XCR0 and EDX:EAX select, such as the x87, SSE and AVX registers, to a 64-byte aligned XSAVE area.	2
XSETBV	Writes EDX:EAX to the extended control register that ECX selects, such as XCR0, which enables AVX and other XSAVE state; ring 0 only.	1

CPUID and processors

XED splits XSAVE into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of XSAVE. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`XSAVE` XSAVE	XSAVE + OSXSAVE `CPUID.01H:ECX[26]` XSAVE `CPUID.01H:ECX[27]` OSXSAVE	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Instructions

CPUID and processors

Sources