x86-64.net

System

XSAVEC

XSAVEC saves processor state in the compacted format, which packs the selected components together and leaves out those in their initial state.

CPUID
XSAVEC
CPUID.(EAX=0DH,ECX=1):EAX[1]
Instructions
1 mnemonic
Processors
Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

XSAVEC saves in the compacted format of the XSAVE area: instead of each component at the fixed offset that CPUID leaf 0DH gives, the selected components follow each other, so the area is only as large as the components in use. Components in their initial state are not written at all; the header records which ones were saved and that the area is compacted, and XRSTOR reads either format. Unlike XSAVEOPT, it writes every selected component that is not in its initial state, changed or not.

Instructions

Mnemonics with at least one form in XSAVEC. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
XSAVECSaves selected state components in the compacted format of the XSAVE area, leaving out those in their initial state.2

CPUID and processors

XED splits XSAVEC into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of XSAVEC. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
XSAVEC

XSAVEC
CPUID.(EAX=0DH,ECX=1):EAX[1] XSAVEC

Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.