x86-64.net

System

XSAVEOPT

XSAVEOPT saves like XSAVE but may skip state components that have not changed since the last XRSTOR or are in their initial state, which saves time on context switches.

CPUID
XSAVEOPT
CPUID.(EAX=0DH,ECX=1):EAX[0]
Instructions
1 mnemonic
Processors
Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

XSAVEOPT saves the same components to the same standard-format area as XSAVE, but may skip two kinds of them: those in their initial state, which the area’s header then marks as such, and those that have not changed since the last XRSTOR loaded them from the same area. The processor tracks both, so a kernel that saves a thread’s state to the area it last restored it from writes only what the thread changed. The area must not be changed in between, since the skipped parts are the ones already in memory.

Instructions

Mnemonics with at least one form in XSAVEOPT. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
XSAVEOPTSaves selected state components like XSAVE but may skip those unchanged since the last XRSTOR or in their initial state.2

CPUID and processors

XED splits XSAVEOPT into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of XSAVEOPT. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
XSAVEOPT

XSAVEOPT
CPUID.(EAX=0DH,ECX=1):EAX[0] XSAVEOPT

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.