x86-64.net

System

XSAVES

XSAVES and XRSTORS save and restore supervisor state components, such as the Processor Trace and CET registers, together with user state, in the compacted format; ring 0 only.

CPUID
XSAVES
CPUID.(EAX=0DH,ECX=1):EAX[3]
Instructions
2 mnemonics
Processors
Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Some state components belong to the operating system, such as the Processor Trace MSRs and CET’s shadow-stack pointers. Only XSAVES and XRSTORS save and restore those: the kernel enables them in the IA32_XSS MSR, as XCR0 enables user components, and both instructions run only at privilege level 0. XSAVES writes the compacted format and skips components that are in their initial state or unchanged since the last XRSTORS, combining what XSAVEC and XSAVEOPT do. The forms with REX.W store the x87 pointers as 64-bit values, as with XSAVE.

Instructions

Mnemonics with at least one form in XSAVES. Each page lists all forms of the mnemonic, including those of other extensions.
MnemonicSummaryForms
XRSTORSRestores user and supervisor state components from a compacted XSAVE area written by XSAVES; ring 0 only.2
XSAVESSaves selected user and supervisor state components in the compacted format, skipping unchanged and initial ones; ring 0 only.2

CPUID and processors

XED splits XSAVES into 1 ISA set. Software can use a form when the processor reports every CPUID bit of one alternative of the form's ISA set.

XED ISA sets of XSAVES. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
XSAVES

XSAVES
CPUID.(EAX=0DH,ECX=1):EAX[3] XSAVES

Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.