x86 命令リファレンス
汎用命令のベースから最新の拡張までの x86 命令を、すべての命令形式の構文、エンコーディング、CPUID 要件、プロセッサーとともに示します。
このリファレンスは ISA 拡張に挙げた拡張を扱います。汎用命令とシステム命令、およびその周辺の CMOV、BMI1、XSAVE、CET、SYSCALL などの小さなセット、x87 と MMX、SSE から SSE4.2、AVX と AVX2、AVX10.1 と AVX10.2 およびその周辺の VEX 拡張、AMX ファミリと ACE、APX、仮想化とセキュリティの拡張である VMX、TDX、SMX、SGX、FRED や新しい MSR 命令などのシステム命令、Xeon Phi の拡張、3DNow!、SSE4a、XOP、FMA4、TBM から SVM、SEV-SNP までの AMD 独自の拡張、そして VIA の PadLock です。これらを合わせると Intel XED がデコードするすべての命令を網羅し、すべてのニーモニックに、そのすべての命令形式を挙げたページがあります。レジスターの値によって選ばれる複数の操作のうち 1 つを実行する命令は、それらのリーフを挙げており、各リーフにも GETSEC[SENTER] や、SGX エンクレーブを開始する ENCLS のリーフである ECREATE のように専用のページがあります。下の表では、リーフはその命令の後に続きます。
構文、エンコーディング、CPUID ビット、プロセッサーの一覧は、Intel が Apache License 2.0 で公開しているエンコーダーおよびデコーダーのライブラリである Intel XED から生成しています。要約の文と詳しい説明は独自のものです。Intel のマニュアルが命令を説明している場合、その命令のページの出典に、説明が始まるマニュアルのページへのリンクがあります。
命令のページには、その命令にコンパイルされる C の組み込み関数も、それぞれがコンパイルされる正確な命令形式とともに挙げています。これは Clang のヘッダーから取り、すべての組み込み関数をコンパイルして確認したものです。x86 組み込み関数 A–Z の索引にそのすべてを挙げています。
ベクトル命令のほとんどは、#UD、#GP、#PF などの例外を他の多くの命令と共有する規則に従って発生させます。Intel のマニュアルはこれを例外クラスと呼び、XED はすべての命令形式について記録しています。例外クラスでは、各クラスをプロセッサーモードごとに独自の言葉で説明し、そのクラスに属する命令を挙げています。
このデータはすべて insn.json (4.9 MB) としてダウンロードできます。その形式とライセンスは about ページで説明しています。
| ニーモニック | 要約 | 拡張 |
|---|---|---|
| AAA | Corrects AL after adding two unpacked BCD digits: if the low digit exceeds 9 or AF is set, adds 6 to AL and 1 to AH and sets CF and AF; not in 64-bit mode. | General-purpose |
| AAD | Turns the unpacked BCD digits in AH and AL into the binary number AL plus AH times the immediate base (10 as assembled) before a DIV; not in 64-bit mode. | General-purpose |
| AADD | Atomically adds a register to a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| AAM | Splits AL into two unpacked BCD digits after a MUL: AH gets AL divided by the immediate base (10 as assembled), AL the remainder; not in 64-bit mode. | General-purpose |
| AAND | Atomically ANDs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| AAS | Corrects AL after subtracting two unpacked BCD digits: if the low digit exceeds 9 or AF is set, subtracts 6 from AX and 1 from AH; not in 64-bit mode. | General-purpose |
| ADC | Adds two integers and the carry flag, the step that chains multi-word additions; APX adds a three-operand form. | General-purpose, APX |
| ADCX | Adds two unsigned integers and the carry flag and changes only CF, so a carry chain can run next to an ADOX chain; APX adds a three-operand form. | ADX, APX |
| ADD | Adds two integers and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ADDPD | Adds two packed doubles of the source to those of the destination XMM register. | SSE2 |
| ADDPS | Adds four packed singles of the source to those of the destination XMM register. | SSE |
| ADDSD | Adds the low double of the source to the low double of the destination; the upper half of the destination is kept. | SSE2 |
| ADDSS | Adds the low single of the source to the low single of the destination; the upper three elements are kept. | SSE |
| ADDSUBPD | Subtracts in the low double and adds in the high double, the step of complex multiplication; SSE3. | SSE3 |
| ADDSUBPS | Subtracts in the even-numbered singles and adds in the odd-numbered ones, the step of complex multiplication; SSE3. | SSE3 |
| ADOX | Adds two unsigned integers and the overflow flag and changes only OF, so a carry chain can run next to an ADCX chain; APX adds a three-operand form. | ADX, APX |
| AESDEC | Performs one round of AES decryption on the block in an XMM register with the round key of the source. | AES-NI |
| AESDEC128KL | Decrypts the block in an XMM register with ten AES rounds, using the 128-bit key of a Key Locker handle in memory; ZF=1 reports a bad handle. | Key Locker |
| AESDEC256KL | Decrypts the block in an XMM register with 14 AES rounds, using the 256-bit key of a Key Locker handle in memory; ZF=1 reports a bad handle. | Key Locker |
| AESDECLAST | Performs the last round of AES decryption, without InvMixColumns, on a block with the round key of the source. | AES-NI |
| AESDECWIDE128KL | Decrypts eight blocks in XMM0 to XMM7 with ten AES rounds, using the 128-bit key of a Key Locker handle in memory; ZF=1 if the handle fails. | Key Locker |
| AESDECWIDE256KL | Decrypts eight blocks in XMM0 to XMM7 with 14 AES rounds, using the 256-bit key of a Key Locker handle in memory; ZF=1 if the handle fails. | Key Locker |
| AESENC | Performs one round of AES encryption on the block in an XMM register with the round key of the source. | AES-NI |
| AESENC128KL | Encrypts the block in an XMM register with ten AES rounds, using the 128-bit key of a Key Locker handle in memory; ZF=1 reports a bad handle. | Key Locker |
| AESENC256KL | Encrypts the block in an XMM register with 14 AES rounds, using the 256-bit key of a Key Locker handle in memory; ZF=1 reports a bad handle. | Key Locker |
| AESENCLAST | Performs the last round of AES encryption, without MixColumns, on a block with the round key of the source. | AES-NI |
| AESENCWIDE128KL | Encrypts eight blocks in XMM0 to XMM7 with ten AES rounds, using the 128-bit key of a Key Locker handle in memory; ZF=1 if the handle fails. | Key Locker |
| AESENCWIDE256KL | Encrypts eight blocks in XMM0 to XMM7 with 14 AES rounds, using the 256-bit key of a Key Locker handle in memory; ZF=1 if the handle fails. | Key Locker |
| AESIMC | Applies InvMixColumns to an AES round key, turning encryption round keys into those of the equivalent decryption. | AES-NI |
| AESKEYGENASSIST | Computes the substituted and rotated words, with a round constant from an immediate, that AES key expansion needs. | AES-NI |
| AND | Computes the bitwise AND of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ANDN | Computes the bitwise AND of the inverted first source with the second source into a separate destination; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| ANDNPD | Computes the bitwise AND of the inverted destination with the source, as packed doubles. | SSE2 |
| ANDNPS | Computes the bitwise AND of the inverted destination with the source, as packed singles. | SSE |
| ANDPD | Computes the bitwise AND of two XMM operands, as packed doubles. | SSE2 |
| ANDPS | Computes the bitwise AND of two XMM operands, as packed singles. | SSE |
| AOR | Atomically ORs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| ARPL | Raises the requested privilege level of a segment selector to that of another, setting ZF if it changed; not in 64-bit mode, where 63 is MOVSXD. | System |
| AXOR | Atomically XORs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| BEXTR | Extracts a bit field whose start and length come from a second register; APX adds a form that leaves the flags unchanged. | BMI1, APX, TBM |
| BLCFILL | Clears the bits below the lowest clear bit of a general-purpose register or memory (x & (x + 1)); TBM. | TBM |
| BLCI | Sets every bit but the lowest clear bit of the source (x | ~(x + 1)); TBM. | TBM |
| BLCIC | Isolates the lowest clear bit of the source as the only set bit (~x & (x + 1)); TBM. | TBM |
| BLCMSK | Makes a mask of the lowest clear bit of the source and the bits below it (x ^ (x + 1)); TBM. | TBM |
| BLCS | Sets the lowest clear bit of the source (x | (x + 1)); TBM. | TBM |
| BLENDPD | Picks each double from the destination or the source, as a bit of an immediate says; SSE4.1. | SSE4.1 |
| BLENDPS | Picks each single from the destination or the source, as a bit of an immediate says; SSE4.1. | SSE4.1 |
| BLENDVPD | Picks each double from the destination or the source by the sign bit of the matching element of XMM0; SSE4.1. | SSE4.1 |
| BLENDVPS | Picks each single from the destination or the source by the sign bit of the matching element of XMM0; SSE4.1. | SSE4.1 |
| BLSFILL | Sets the bits below the lowest set bit of the source (x | (x - 1)); TBM. | TBM |
| BLSI | Isolates the lowest set bit of the source, clearing all others; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BLSIC | Clears the lowest set bit of the source and sets every other bit (~x | (x - 1)); TBM. | TBM |
| BLSMSK | Sets all bits up to and including the lowest set bit of the source and clears the rest; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BLSR | Clears the lowest set bit of the source; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BNDCL | Raises a bound-range exception (#BR) if an address is below the lower bound in an MPX bound register; MPX has been removed. | MPX |
| BNDCN | Raises #BR if an address is above the upper bound of an MPX bound register, taken as stored rather than complemented as BNDCU does; MPX has been removed. | MPX |
| BNDCU | Raises #BR if an address is above the upper bound of an MPX bound register, which keeps it in one's complement; MPX has been removed. | MPX |
| BNDLDX | Loads the MPX bounds of a pointer from the bound tables in memory, found by the address the pointer is stored at; MPX has been removed. | MPX |
| BNDMK | Makes MPX bounds from a memory operand: the lower bound from its base, the upper from its address; MPX has been removed. | MPX |
| BNDMOV | Copies MPX bounds between bound registers, or between a bound register and memory; MPX has been removed. | MPX |
| BNDSTX | Stores the MPX bounds of a pointer into the bound tables in memory, found by the address the pointer is stored at; MPX has been removed. | MPX |
| BOUND | Raises a bound-range exception (#BR) unless a signed array index in a register lies within the two bounds stored in memory; not in 64-bit mode. | General-purpose |
| BSF | Writes the index of the lowest set bit of the source to the destination; a zero source sets ZF and leaves the destination unchanged. | General-purpose |
| BSR | Writes the index of the highest set bit of the source to the destination; a zero source sets ZF and leaves the destination unchanged. | General-purpose |
| BSRINIT | ACE instruction that sets every byte of the block scale register to 7FH, the E8M0 encoding of a scale factor of 1.0. | ACE |
| BSRMOVF | ACE instruction that loads all 1024 bits of the block scale register from two ZMM sources, the first giving the upper half. | ACE |
| BSRMOVH | ACE instruction that moves the upper 512 bits of the block scale register to or from a ZMM register or memory. | ACE |
| BSRMOVL | ACE instruction that moves the lower 512 bits of the block scale register to or from a ZMM register or memory. | ACE |
| BSWAP | Reverses the byte order of a 32- or 64-bit register, converting between little- and big-endian values; with a 16-bit register the result is undefined. | General-purpose |
| BT | Copies the bit that a register or immediate offset selects in a register or memory operand into CF; a register offset can reach beyond a memory operand. | General-purpose |
| BTC | Copies the selected bit of a register or memory operand into CF and then inverts it; with LOCK the memory form is atomic. | General-purpose |
| BTR | Copies the selected bit of a register or memory operand into CF and then clears it; with LOCK the memory form is atomic. | General-purpose |
| BTS | Copies the selected bit of a register or memory operand into CF and then sets it; with LOCK the memory form is an atomic test-and-set. | General-purpose |
| BZHI | Clears the bits of the source from a given bit position upward; APX adds a form that leaves the flags unchanged. | BMI2, APX |
| CALL | Pushes the return address and jumps to a relative target, one in a register or memory, or a far pointer that also changes the code segment. | General-purpose |
| CBW | Sign-extends AL into AX, copying bit 7 of AL into every bit of AH (AT&T cbtw). | General-purpose |
| CCMPscc | APX conditional compare: if the flags meet a condition, compares two operands, otherwise sets OF, SF, ZF and CF to a value in the instruction. | APX |
| CDQ | Sign-extends EAX into EDX:EAX, filling EDX with the sign bit of EAX, typically before a 32-bit IDIV (AT&T cltd). | General-purpose |
| CDQE | Sign-extends EAX into RAX in 64-bit mode; compilers emit it, as cltq in AT&T syntax, to widen a signed 32-bit value. | General-purpose |
| CFCMOVcc | APX conditionally faulting move: on a false condition, memory is untouched and cannot fault; a register destination gets zero, or a source with NDD. | APX |
| CLAC | Clears the alignment-check flag (AC), so that SMAP again stops the kernel from touching user pages; ring 0 only. | SMAP |
| CLC | Clears the carry flag (CF). | General-purpose |
| CLD | Clears the direction flag (DF), so that string instructions step upward through memory; the System V and Microsoft ABIs require it clear at calls. | General-purpose |
| CLDEMOTE | Hints that the cache line holding a byte of memory should move from the core's caches to a more distant level, where other cores reach it sooner. | CLDEMOTE |
| CLFLUSH | Writes back and invalidates the cache line holding a byte of memory in every cache of the coherence domain, ordered with writes and other CLFLUSHes. | CLFLUSH |
| CLFLUSHOPT | Writes back and invalidates the cache line holding a byte of memory like CLFLUSH, but unordered with flushes of other lines, so several can overlap. | CLFLUSHOPT |
| CLGI | Clears the global interrupt flag (GIF), which holds off all external interrupts; AMD SVM. | SVM |
| CLI | Clears the interrupt flag (IF) to hold off maskable interrupts; where CPL is above IOPL it faults or clears the virtual interrupt flag instead. | General-purpose |
| CLRSSBSY | Clears the busy flag of a supervisor shadow-stack token in memory and zeroes the shadow-stack pointer; not with FRED. | CET |
| CLTS | Clears the task-switched flag (TS) in CR0, which trapped the first x87 or SSE use after a task switch; ring 0 only. | System |
| CLUI | Clears the user interrupt flag (UIF), holding user interrupts back from the next instruction on. | UINTR |
| CLWB | Writes the cache line holding a byte of memory back if it was modified and may keep it cached, for example to make stores to persistent memory durable. | CLWB |
| CLZERO | Writes zeros to the whole cache line that contains the address in rAX. | CLZERO |
| CMC | Inverts the carry flag (CF). | General-purpose |
| CMOVcc | Copies the source to a register if a condition on the flags holds; APX adds a three-operand form that picks one of two sources. | CMOV, APX |
| CMP | Compares two operands by subtracting the second from the first, setting the arithmetic flags as SUB would and discarding the result. | General-purpose |
| CMPccXADD | Atomically compares memory with a register, adds a second register to memory if the condition holds, and returns the old value in the first. | CMPccXADD, APX |
| CMPPD | Compares two packed doubles with one of eight predicates an immediate selects, into all-ones or all-zeros elements. | SSE2 |
| CMPPS | Compares four packed singles with one of eight predicates an immediate selects, into all-ones or all-zeros elements. | SSE |
| CMPS | Compares the element at [RSI] with the one at [RDI], setting the flags as CMP would, and steps both pointers; REPE and REPNE repeat it. | General-purpose |
| CMPSD | Compares the low doubles with one of eight predicates an immediate selects, into an all-ones or all-zeros element. | SSE2 |
| CMPSS | Compares the low singles with one of eight predicates an immediate selects, into an all-ones or all-zeros element. | SSE |
| CMPXCHG | Compares the accumulator with the destination: if equal, stores the source there and sets ZF, else loads the destination; atomic with LOCK. | General-purpose |
| CMPXCHG16B | Compares RDX:RAX with 16 aligned bytes of memory: if equal, stores RCX:RBX there and sets ZF, else loads them into RDX:RAX; atomic with LOCK. | CMPXCHG16B |
| CMPXCHG8B | Compares EDX:EAX with 8 bytes of memory: if equal, stores ECX:EBX there and sets ZF, else loads them into EDX:EAX; atomic with LOCK. | General-purpose |
| COMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN raises an invalid exception. | SSE2 |
| COMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN raises an invalid exception. | SSE |
| CPUID | Returns identification and feature information about the processor in EAX, EBX, ECX and EDX, for the leaf in EAX and the sub-leaf in ECX. | General-purpose |
| CQO | Sign-extends RAX into RDX:RAX, filling RDX with the sign bit of RAX, typically before a 64-bit IDIV (AT&T cqto); 64-bit mode only. | General-purpose |
| CRC32 | Accumulates a CRC-32C checksum (Castagnoli polynomial) over a 1-, 2-, 4- or 8-byte operand. | SSE4.2, APX |
| CTESTscc | APX conditional test: if the flags meet a condition, tests two operands with AND, otherwise sets OF, SF, ZF and CF to a value in the instruction. | APX |
| CVTDQ2PD | Converts the two low signed doublewords of the source to doubles. | SSE2 |
| CVTDQ2PS | Converts four packed signed doublewords to singles, rounding as MXCSR says. | SSE2 |
| CVTPD2DQ | Converts two packed doubles to signed doublewords in the low half, rounding as MXCSR says and zeroing the high half. | SSE2 |
| CVTPD2PI | Converts two packed doubles to signed doublewords in an MMX register, rounding as MXCSR says. | SSE2 |
| CVTPD2PS | Converts two packed doubles to singles in the low half, rounding as MXCSR says and zeroing the high half. | SSE2 |
| CVTPI2PD | Converts two signed doublewords from an MMX register or memory to doubles. | SSE2 |
| CVTPI2PS | Converts two signed doublewords from an MMX register or memory to the low two singles of an XMM register. | SSE |
| CVTPS2DQ | Converts four packed singles to signed doublewords, rounding as MXCSR says. | SSE2 |
| CVTPS2PD | Converts the two low singles of the source to doubles, which is exact. | SSE2 |
| CVTPS2PI | Converts the two low singles to signed doublewords in an MMX register, rounding as MXCSR says. | SSE |
| CVTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR says. | SSE2 |
| CVTSD2SS | Converts the low double of the source to single, rounding as MXCSR says; the other elements of the destination are kept. | SSE2 |
| CVTSI2SD | Converts a signed 32- or 64-bit integer to double in the low element; the upper half of the destination is kept. | SSE2 |
| CVTSI2SS | Converts a signed 32- or 64-bit integer to single in the low element; the other elements of the destination are kept. | SSE |
| CVTSS2SD | Converts the low single of the source to double, which is exact; the upper half of the destination is kept. | SSE2 |
| CVTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR says. | SSE |
| CVTTPD2DQ | Converts two packed doubles to signed doublewords in the low half, truncating toward zero and zeroing the high half. | SSE2 |
| CVTTPD2PI | Converts two packed doubles to signed doublewords in an MMX register, truncating toward zero. | SSE2 |
| CVTTPS2DQ | Converts four packed singles to signed doublewords, truncating toward zero. | SSE2 |
| CVTTPS2PI | Converts the two low singles to signed doublewords in an MMX register, truncating toward zero. | SSE |
| CVTTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | SSE2 |
| CVTTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | SSE |
| CWD | Sign-extends AX into DX:AX, filling DX with the sign bit of AX, typically before a 16-bit IDIV (AT&T cwtd). | General-purpose |
| CWDE | Sign-extends AX into EAX (AT&T cwtl); in 64-bit mode the write to EAX also clears the upper half of RAX. | General-purpose |
| DAA | Corrects AL after adding two packed BCD numbers so that it holds two decimal digits, setting CF on a decimal carry; not in 64-bit mode. | General-purpose |
| DAS | Corrects AL after subtracting two packed BCD numbers so that it holds two decimal digits, setting CF on a decimal borrow; not in 64-bit mode. | General-purpose |
| DEC | Subtracts one from an operand without changing the carry flag; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| DIV | Divides an unsigned double-width dividend in rDX:rAX (AX for bytes) by the operand into quotient and remainder; APX adds a form that keeps the flags. | General-purpose, APX |
| DIVPD | Divides the two packed doubles of the destination XMM register by those of the source. | SSE2 |
| DIVPS | Divides the four packed singles of the destination XMM register by those of the source. | SSE |
| DIVSD | Divides the low double of the destination by the low double of the source; the upper half is kept. | SSE2 |
| DIVSS | Divides the low single of the destination by the low single of the source; the upper three elements are kept. | SSE |
| DPPD | Computes a dot product of the packed doubles, with an immediate choosing which products to add and where the sum goes. | SSE4.1 |
| DPPS | Computes a dot product of the packed singles, with an immediate choosing which products to add and where the sum goes. | SSE4.1 |
| EMMS | Marks every x87 register empty at the end of MMX code, so that x87 instructions can use the register stack again. | MMX |
| ENCLS | Performs the SGX leaf function for the operating system that EAX selects, such as ECREATE or EADD; only CPL 0 may run it. | SGX |
| ECREATE | Starts building an enclave by copying its control structure, the SECS, from ordinary memory into a page of the EPC. | SGX |
| EADD | Copies a page from ordinary memory into the EPC for an enclave being built, and adds its offset and attributes to the enclave's measurement. | SGX |
| EINIT | Completes the build of an enclave: checks its signed SIGSTRUCT and launch token, fixes its measurement and makes it ready for EENTER. | SGX |
| EREMOVE | Removes a page from the EPC, detaching it from its enclave and marking it unused. | SGX |
| EDBGRD | Reads eight bytes (four outside 64-bit mode) of a debug enclave's memory, at the address in RCX, into RBX. | SGX |
| EDBGWR | Writes RBX (EBX outside 64-bit mode) to a debug enclave's memory at the address in RCX. | SGX |
| EEXTEND | Adds 256 bytes of a page of an enclave being built to the enclave's measurement, MRENCLAVE. | SGX |
| ELDB | Loads a page that EWB wrote out back into the EPC, checking and decrypting it, and marks it blocked. | SGX |
| ELDU | Loads a page that EWB wrote out back into the EPC, checking and decrypting it, and leaves it unblocked. | SGX |
| EBLOCK | Marks an EPC page as blocked, the first step of evicting it from the EPC. | SGX |
| EPA | Turns an EPC page into a version array, which holds the versions of pages evicted from the EPC. | SGX |
| EWB | Evicts a blocked EPC page: encrypts it, writes it to ordinary memory and keeps its version in a version array. | SGX |
| ETRACK | Starts tracking the TLB flushes that must follow EBLOCK before the blocked pages of an enclave can be evicted. | SGX |
| EAUG | Adds a zeroed page to an enclave that is already running; the enclave must accept it with EACCEPT or EACCEPTCOPY. | SGX |
| EMODPR | Restricts the access rights of a page of a running enclave, which then accepts the change with EACCEPT. | SGX |
| EMODT | Changes the type of a page of a running enclave, to trim it for example, which then accepts the change with EACCEPT. | SGX |
| EUPDATESVN | Updates the SGX security version of the processor to that of the loaded microcode update, when the EPC holds no valid page. | SGX |
| ENCLU | Performs the SGX leaf function for applications and enclaves that EAX selects, such as EENTER or EGETKEY; only CPL 3 may run it. | SGX |
| EREPORT | Creates a report of the running enclave that a target enclave on the same platform can verify, for local attestation. | SGX |
| EGETKEY | Returns a 128-bit key from the processor's key hierarchy, such as a sealing key, as a KEYREQUEST structure asks. | SGX |
| EENTER | Enters an enclave through one of its thread control structures (TCS), at the entry point that the TCS gives. | SGX |
| ERESUME | Re-enters an enclave that an exception or interrupt left, with the state saved in its SSA frame. | SGX |
| EEXIT | Leaves the running enclave and continues at the address in RBX, outside it. | SGX |
| EACCEPT | Lets a running enclave accept a change that system software made to one of its pages with EAUG, EMODT or EMODPR. | SGX |
| EMODPE | Extends the access rights of a page of the running enclave, which the enclave may do by itself. | SGX |
| EACCEPTCOPY | Initializes a page that EAUG added by copying another page of the enclave into it, and accepts it. | SGX |
| EVERIFYREPORT2 | Checks, inside an enclave, the MAC of a report that a TDX trust domain created with SEAMREPORT. | SGX |
| EDECCSSA | Decrements the index of the current SSA frame (TCS.CSSA) of the enclave thread, from inside the enclave. | SGX |
| ENCLV | Performs the SGX virtualization leaf function that EAX selects; XED decodes it, but Intel's manual of September 2026 no longer documents it. | SGX |
| ENCODEKEY128 | Wraps the 128-bit AES key in XMM0 into a Key Locker handle in XMM0 to XMM2, so that software can discard the key itself. | Key Locker |
| ENCODEKEY256 | Wraps the 256-bit AES key in XMM0 and XMM1 into a Key Locker handle in XMM0 to XMM3, so that software can discard the key itself. | Key Locker |
| ENDBR32 | Marks a valid target of an indirect call or jump in 32-bit code for CET indirect branch tracking; a NOP on other processors. | CET |
| ENDBR64 | Marks a valid target of an indirect call or jump in 64-bit code for CET indirect branch tracking; a NOP on other processors. | CET |
| ENQCMD | Sends a 64-byte command, tagged with the PASID from the IA32_PASID MSR, to a device's enqueue register and sets ZF if the device did not accept it. | ENQCMD, APX |
| ENQCMDS | Kernel version of ENQCMD that takes the PASID and privilege bit of the 64-byte command from its memory operand instead of the IA32_PASID MSR. | ENQCMD, APX |
| ENTER | Makes a stack frame: pushes the frame pointer, copies outer frame pointers for nested procedures, and reserves the given bytes of locals. | General-purpose |
| ERETS | Returns from a FRED event handler to code that also runs in ring 0, restoring the interrupted context from the stack. | FRED |
| ERETU | Returns from a FRED event handler in ring 0 to ring 3, restoring the user context from the stack and swapping the GS base with IA32_KERNEL_GS_BASE. | FRED |
| EXTRACTPS | Copies the single that an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1. | SSE4.1 |
| EXTRQ | Extracts a bit field, whose length and position an immediate or a register gives, from the low quadword of an XMM register; SSE4a. | SSE4a |
| F2XM1 | Replaces ST(0), which must lie between -1 and +1, with 2 to the power ST(0), minus 1. | x87 |
| FABS | Clears the sign bit of ST(0), leaving its absolute value. | x87 |
| FADD | Adds a 32- or 64-bit float from memory to ST(0), or adds ST(0) and ST(i) into either of them. | x87 |
| FADDP | Adds ST(0) to ST(i), stores the sum in ST(i) and pops the register stack. | x87 |
| FBLD | Converts an 18-digit packed BCD integer from 10 bytes of memory to extended precision and pushes it. | x87 |
| FBSTP | Rounds ST(0) to an integer, stores it as 18-digit packed BCD in 10 bytes of memory and pops the register stack. | x87 |
| FCHS | Inverts the sign bit of ST(0). | x87 |
| FCMOVB | Copies ST(i) to ST(0) if CF is set (below, after FCOMI or an integer compare). | x87 |
| FCMOVBE | Copies ST(i) to ST(0) if CF or ZF is set (below or equal). | x87 |
| FCMOVE | Copies ST(i) to ST(0) if ZF is set (equal). | x87 |
| FCMOVNB | Copies ST(i) to ST(0) if CF is clear (not below). | x87 |
| FCMOVNBE | Copies ST(i) to ST(0) if both CF and ZF are clear (above). | x87 |
| FCMOVNE | Copies ST(i) to ST(0) if ZF is clear (not equal). | x87 |
| FCMOVNU | Copies ST(i) to ST(0) if PF is clear, which after FCOMI means the operands were ordered (neither was a NaN). | x87 |
| FCMOVU | Copies ST(i) to ST(0) if PF is set, which after FCOMI means the comparison was unordered (a NaN). | x87 |
| FCOM | Compares ST(0) with ST(i) or a 32- or 64-bit float in memory and sets C0, C2 and C3 of the x87 status word; any NaN is an invalid operation. | x87 |
| FCOMI | Compares ST(0) with ST(i) and sets ZF, PF and CF in EFLAGS directly; any NaN is an invalid operation. | x87 |
| FCOMIP | Compares ST(0) with ST(i) like FCOMI, setting ZF, PF and CF, then pops the register stack. | x87 |
| FCOMP | Compares ST(0) with ST(i) or a float in memory like FCOM, then pops the register stack. | x87 |
| FCOMPP | Compares ST(0) with ST(1) like FCOM, then pops the register stack twice. | x87 |
| FCOS | Replaces ST(0), an angle in radians of magnitude below 2^63, with its cosine; C2 reports an operand out of range. | x87 |
| FDECSTP | Subtracts one from the TOP field of the x87 status word, rotating the register stack without moving any data. | x87 |
| FDIV | Divides ST(0) by a float from memory, or ST(0) by ST(i) or ST(i) by ST(0), into the dividend's register. | x87 |
| FDIVP | Divides ST(i) by ST(0), stores the quotient in ST(i) and pops the register stack. | x87 |
| FDIVR | Divides a float from memory by ST(0), or ST(i) by ST(0) into ST(0), or ST(0) by ST(i) into ST(i): FDIV with the operands swapped. | x87 |
| FDIVRP | Divides ST(0) by ST(i), stores the quotient in ST(i) and pops the register stack. | x87 |
| FEMMS | Marks every x87 register empty at the end of 3DNow! or MMX code, exactly as EMMS does; AMD keeps it for older software. | 3DNow! |
| FFREE | Marks ST(i) as empty in the x87 tag word, without changing the stack top. | x87 |
| FFREEP | Marks ST(i) as empty and pops the register stack; Intel's manual does not list it, but XED decodes it. | x87 |
| FIADD | Adds a 16- or 32-bit signed integer from memory to ST(0). | x87 |
| FICOM | Compares ST(0) with a 16- or 32-bit signed integer in memory and sets C0, C2 and C3 of the x87 status word. | x87 |
| FICOMP | Compares ST(0) with a 16- or 32-bit signed integer in memory like FICOM, then pops the register stack. | x87 |
| FIDIV | Divides ST(0) by a 16- or 32-bit signed integer from memory. | x87 |
| FIDIVR | Divides a 16- or 32-bit signed integer from memory by ST(0), into ST(0). | x87 |
| FILD | Converts a 16-, 32- or 64-bit signed integer from memory to extended precision and pushes it. | x87 |
| FIMUL | Multiplies ST(0) by a 16- or 32-bit signed integer from memory. | x87 |
| FINCSTP | Adds one to the TOP field of the x87 status word, rotating the register stack without freeing a register. | x87 |
| FIST | Converts ST(0) to a 16- or 32-bit signed integer, rounded as the control word says, and stores it in memory. | x87 |
| FISTP | Converts ST(0) to a 16-, 32- or 64-bit signed integer as the rounding control says, stores it and pops the register stack. | x87 |
| FISTTP | Stores ST0 as a signed 16-, 32- or 64-bit integer, truncating toward zero whatever the rounding mode, and pops it; SSE3. | SSE3 |
| FISUB | Subtracts a 16- or 32-bit signed integer in memory from ST(0). | x87 |
| FISUBR | Subtracts ST(0) from a 16- or 32-bit signed integer in memory, into ST(0). | x87 |
| FLD | Pushes a 32-, 64- or 80-bit float from memory, or a copy of ST(i), onto the x87 register stack. | x87 |
| FLD1 | Pushes the constant +1.0 onto the x87 register stack. | x87 |
| FLDCW | Loads the x87 control word (exception masks, precision and rounding control) from 16 bits of memory. | x87 |
| FLDENV | Loads the x87 environment (control, status and tag words and the last instruction and operand pointers) from memory. | x87 |
| FLDL2E | Pushes the constant log2(e) onto the x87 register stack. | x87 |
| FLDL2T | Pushes the constant log2(10) onto the x87 register stack. | x87 |
| FLDLG2 | Pushes the constant log10(2) onto the x87 register stack. | x87 |
| FLDLN2 | Pushes the constant ln(2) onto the x87 register stack. | x87 |
| FLDPI | Pushes the constant pi onto the x87 register stack. | x87 |
| FLDZ | Pushes the constant +0.0 onto the x87 register stack. | x87 |
| FMUL | Multiplies ST(0) by a float from memory, or ST(0) and ST(i) into either of them. | x87 |
| FMULP | Multiplies ST(i) by ST(0), stores the product in ST(i) and pops the register stack. | x87 |
| FNCLEX | Clears the x87 exception flags without first handling pending exceptions; FCLEX is FWAIT followed by it. | x87 |
| FNDISI | An 8087 instruction that masked the coprocessor's interrupt; later x87 units ignore it, and XED decodes it as a no-op. | x87 |
| FNENI | An 8087 instruction that unmasked the coprocessor's interrupt; later x87 units ignore it, and XED decodes it as a no-op. | x87 |
| FNINIT | Resets the x87 unit to its default state without first handling pending exceptions; FINIT is FWAIT followed by it. | x87 |
| FNOP | Does nothing apart from updating the x87 instruction pointer. | x87 |
| FNSAVE | Stores the x87 environment and the eight data registers to memory, then resets the unit like FNINIT; FSAVE is FWAIT followed by it. | x87 |
| FNSETPM | An 80287 instruction that put the coprocessor in protected mode; later x87 units ignore it, and XED decodes it as a no-op. | x87 |
| FNSTCW | Stores the x87 control word to 16 bits of memory; FSTCW is FWAIT followed by it. | x87 |
| FNSTENV | Stores the x87 environment to memory, then masks all x87 exceptions; FSTENV is FWAIT followed by it. | x87 |
| FNSTSW | Stores the x87 status word to 16 bits of memory or to AX; FSTSW is FWAIT followed by it. | x87 |
| FPATAN | Stores the arctangent of ST(1) divided by ST(0), in radians, in ST(1) and pops the register stack. | x87 |
| FPREM | Stores in ST(0) the partial remainder of ST(0) divided by ST(1) with a truncated quotient, as C's fmod gives; C2 says whether to repeat. | x87 |
| FPREM1 | Stores in ST(0) the partial IEEE 754 remainder of ST(0) divided by ST(1), with the quotient rounded to nearest; C2 says whether to repeat. | x87 |
| FPTAN | Replaces ST(0), an angle in radians of magnitude below 2^63, with its tangent and then pushes 1.0. | x87 |
| FRNDINT | Rounds ST(0) to an integral value in the rounding mode of the x87 control word. | x87 |
| FRSTOR | Loads the x87 environment and data registers from memory that FSAVE or FNSAVE stored. | x87 |
| FSCALE | Multiplies ST(0) by 2 to the power of ST(1) truncated to an integer. | x87 |
| FSIN | Replaces ST(0), an angle in radians of magnitude below 2^63, with its sine; C2 reports an operand out of range. | x87 |
| FSINCOS | Replaces ST(0), an angle in radians, with its sine and pushes its cosine, so that ST(0) holds the cosine and ST(1) the sine. | x87 |
| FSQRT | Replaces ST(0) with its square root. | x87 |
| FST | Copies ST(0) to a 32- or 64-bit float in memory, rounding it, or to ST(i). | x87 |
| FSTP | Copies ST(0) to a 32-, 64- or 80-bit float in memory or to ST(i) and pops the register stack. | x87 |
| FSUB | Subtracts a float in memory from ST(0), or ST(i) from ST(0) or ST(0) from ST(i), into the minuend's register. | x87 |
| FSUBP | Subtracts ST(0) from ST(i), stores the difference in ST(i) and pops the register stack. | x87 |
| FSUBR | Subtracts ST(0) from a float in memory, or ST(0) from ST(i) into ST(0), or ST(i) from ST(0) into ST(i): FSUB with the operands swapped. | x87 |
| FSUBRP | Subtracts ST(i) from ST(0), stores the difference in ST(i) and pops the register stack. | x87 |
| FTST | Compares ST(0) with 0.0 and sets C0, C2 and C3 of the x87 status word. | x87 |
| FUCOM | Compares ST(0) with ST(i) and sets C0, C2 and C3 of the x87 status word; only a signaling NaN is an invalid operation. | x87 |
| FUCOMI | Compares ST(0) with ST(i) and sets ZF, PF and CF in EFLAGS; only a signaling NaN is an invalid operation. | x87 |
| FUCOMIP | Compares ST(0) with ST(i) like FUCOMI, setting ZF, PF and CF, then pops the register stack. | x87 |
| FUCOMP | Compares ST(0) with ST(i) like FUCOM, then pops the register stack. | x87 |
| FUCOMPP | Compares ST(0) with ST(1) like FUCOM, then pops the register stack twice. | x87 |
| FWAIT | Waits for the x87 unit and raises any pending unmasked x87 exception; WAIT is another name for it. | x87 |
| FXAM | Classifies ST(0) as empty, zero, normal, denormal, infinity, NaN or unsupported in C0, C2 and C3, with its sign in C1. | x87 |
| FXCH | Exchanges ST(0) with ST(i), ST(1) if no operand is given. | x87 |
| FXRSTOR | Restores the x87, MMX and SSE registers and MXCSR from the 512-byte area that FXSAVE wrote; FXRSTOR64 reads the 64-bit form. | FXSR |
| FXSAVE | Saves the x87, MMX and SSE registers and MXCSR to a 16-byte aligned 512-byte area; FXSAVE64 stores the x87 pointers as 64-bit values. | FXSR |
| FXTRACT | Splits ST(0) into its exponent, left in ST(1), and its significand, pushed as the new ST(0). | x87 |
| FYL2X | Stores ST(1) times log2(ST(0)) in ST(1) and pops the register stack. | x87 |
| FYL2XP1 | Stores ST(1) times log2(ST(0) + 1) in ST(1) and pops; for ST(0) near zero, where it is more accurate than FYL2X. | x87 |
| GETSEC | Performs the Safer Mode Extensions leaf function that EAX selects, such as SENTER, which launches an Intel TXT measured environment. | SMX |
| GETSEC[CAPABILITIES] | Returns a bit for each GETSEC leaf the processor supports and one for an Intel TXT chipset; any privilege level may run it. | SMX |
| GETSEC[ENTERACCS] | Loads the authenticated code module at the physical address in EBX, checks its signature with the chipset's key and runs it. | SMX |
| GETSEC[EXITAC] | Leaves authenticated code execution mode and continues at the address in EBX; an authenticated code module ends with it. | SMX |
| GETSEC[SENTER] | Launches a measured environment: authenticates the module at the physical address in EBX and gathers the other logical processors. | SMX |
| GETSEC[SEXIT] | Ends the measured environment that SENTER launched, signalling every logical processor of the platform. | SMX |
| GETSEC[PARAMETERS] | Returns one SMX parameter per index in EBX, such as the versions of authenticated code modules that the processor accepts. | SMX |
| GETSEC[SMCTRL] | Performs the SMX mode control that EBX selects; the only one, 0, unmasks SMIs after a measured launch. | SMX |
| GETSEC[WAKEUP] | Wakes the other logical processors from the sleep state that the SENTER rendezvous left them in, so that they join the measured environment. | SMX |
| GF2P8AFFINEINVQB | Inverts each byte in GF(2^8), then applies an affine transformation given by an 8x8 bit matrix and an immediate constant. | GFNI |
| GF2P8AFFINEQB | Applies an affine transformation to each byte, given by an 8x8 bit matrix from the source and an immediate constant. | GFNI |
| GF2P8MULB | Multiplies bytes in the finite field GF(2^8) defined by the AES polynomial x^8 + x^4 + x^3 + x + 1. | GFNI |
| HADDPD | Adds the two doubles within each source, the destination's sum going low and the source's high; SSE3. | SSE3 |
| HADDPS | Adds adjacent pairs of singles within each source, the destination's two sums going low and the source's high; SSE3. | SSE3 |
| HLT | Stops the processor until an interrupt, NMI or reset arrives, as an idle loop does; ring 0 only. | System |
| HRESET | Resets the parts of the processor's prediction history that EAX selects and the operating system enabled in IA32_HRESET_ENABLE; allowed only in ring 0. | HRESET |
| HSUBPD | Subtracts the high double from the low one within each source, the destination's result going low; SSE3. | SSE3 |
| HSUBPS | Subtracts the odd single from the even one in adjacent pairs of each source, the destination's results going low; SSE3. | SSE3 |
| IBHF | Indirect branch history fence: in ring 0 with BHI_DIS_S set, stops older branch history from steering later indirect branches; a no-op without BHI_CTRL. | IBHF |
| IDIV | Divides a signed double-width dividend in rDX:rAX (AX for bytes) by the operand into quotient and remainder; APX adds a form that keeps the flags. | General-purpose, APX |
| IMUL | Multiplies signed integers in one-, two- and three-operand forms; APX adds new-destination, flag-preserving and zero-upper immediate forms. | General-purpose, APX |
| IN | Reads a byte, word or doubleword from an I/O port, given as an immediate or in DX, into AL, AX or EAX, if IOPL or the TSS permission bitmap allows. | General-purpose |
| INC | Adds one to an operand without changing the carry flag; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| INCSSPD | Pops and discards the number of 4-byte shadow-stack entries given in the low byte of a register, as unwinding the stack needs; CET. | CET |
| INCSSPQ | Pops and discards the number of 8-byte shadow-stack entries given in the low byte of a register, as unwinding the stack needs; CET. | CET |
| INS | Reads a byte, word or doubleword from the I/O port in DX into memory at [RDI] and steps RDI; REP repeats it RCX times. | General-purpose |
| INSERTPS | Inserts a single from a register or memory into an XMM register at the position an immediate gives, and can zero other elements. | SSE4.1 |
| INSERTQ | Inserts the low bits of one XMM register as a bit field into the low quadword of another; SSE4a. | SSE4a |
| INT | Raises the software interrupt whose vector is the immediate, calling its handler through the IDT, as 32-bit Linux system calls do with INT 80h. | General-purpose |
| INT1 | Raises a debug exception (#DB) with the one-byte opcode F1, meant for hardware debuggers; also known as ICEBP. | General-purpose |
| INT3 | Raises a breakpoint exception (#BP) with the one-byte opcode CC, which debuggers write over an instruction to set a breakpoint. | General-purpose |
| INTO | Raises an overflow exception (#OF) if the overflow flag is set; not in 64-bit mode. | General-purpose |
| INVD | Invalidates the caches without writing modified lines back, so their data is lost; ring 0 only. | System |
| INVEPT | Invalidates cached translations derived from a VMX guest's extended page tables, for one EPT context or all of them. | VMX, APX |
| INVLPG | Invalidates the TLB entries of the page that holds a memory address, after the kernel changed its mapping; ring 0 only. | System |
| INVLPGA | Invalidates the TLB entry of the page at the address in rAX for the address space ID in ECX; AMD SVM. | SVM |
| INVLPGB | Invalidates TLB entries that a descriptor in rAX and EDX selects on every processor of the system, not just this one. | INVLPGB |
| INVPCID | Invalidates TLB entries and paging-structure caches for one address, one process-context identifier or all of them, as the type in a register selects. | INVPCID, APX |
| INVVPID | Invalidates cached translations tagged with a VMX virtual-processor identifier (VPID), for one address, one VPID or all of them. | VMX, APX |
| IRET | Returns from an interrupt or exception handler, popping the instruction pointer, CS and the flags, and in 64-bit mode RSP and SS too. | General-purpose |
| Jcc | Jumps to a relative target if a condition on the flags holds, such as JZ when ZF is set or JL when SF differs from OF. | General-purpose |
| JCXZ | Jumps to a short relative target if CX is zero, without testing or changing the flags; not in 64-bit mode. | General-purpose |
| JECXZ | Jumps to a short relative target if ECX is zero, without testing or changing the flags. | General-purpose |
| JMP | Jumps to a relative target, one in a register or memory, or a far pointer that also changes the code segment. | General-purpose |
| JMPABS | APX jump to a 64-bit absolute address given as an immediate, encoded with a REX2 prefix as an 11-byte instruction. | APX |
| JRCXZ | Jumps to a short relative target if RCX is zero, without testing or changing the flags; 64-bit mode only. | General-purpose |
| KADDB | Adds two 8-bit mask registers as unsigned integers. | AVX10.1 |
| KADDD | Adds two 32-bit mask registers as unsigned integers. | AVX10.1 |
| KADDQ | Adds two 64-bit mask registers as unsigned integers. | AVX10.1 |
| KADDW | Adds two 16-bit mask registers as unsigned integers. | AVX10.1 |
| KANDB | Computes the bitwise AND of two 8-bit masks. | AVX10.1 |
| KANDD | Computes the bitwise AND of two 32-bit masks. | AVX10.1 |
| KANDNB | Computes the bitwise AND of the inverted first 8-bit mask with the second. | AVX10.1 |
| KANDND | Computes the bitwise AND of the inverted first 32-bit mask with the second. | AVX10.1 |
| KANDNQ | Computes the bitwise AND of the inverted first 64-bit mask with the second. | AVX10.1 |
| KANDNW | Computes the bitwise AND of the inverted first 16-bit mask with the second. | AVX10.1 |
| KANDQ | Computes the bitwise AND of two 64-bit masks. | AVX10.1 |
| KANDW | Computes the bitwise AND of two 16-bit masks. | AVX10.1 |
| KMOVB | Moves an 8-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KMOVD | Moves a 32-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KMOVQ | Moves a 64-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KMOVW | Moves a 16-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KNOTB | Inverts every bit of an 8-bit mask. | AVX10.1 |
| KNOTD | Inverts every bit of a 32-bit mask. | AVX10.1 |
| KNOTQ | Inverts every bit of a 64-bit mask. | AVX10.1 |
| KNOTW | Inverts every bit of a 16-bit mask. | AVX10.1 |
| KORB | Computes the bitwise OR of two 8-bit masks. | AVX10.1 |
| KORD | Computes the bitwise OR of two 32-bit masks. | AVX10.1 |
| KORQ | Computes the bitwise OR of two 64-bit masks. | AVX10.1 |
| KORTESTB | ORs two 8-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORTESTD | ORs two 32-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORTESTQ | ORs two 64-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORTESTW | ORs two 16-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORW | Computes the bitwise OR of two 16-bit masks. | AVX10.1 |
| KSHIFTLB | Shifts an 8-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTLD | Shifts a 32-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTLQ | Shifts a 64-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTLW | Shifts a 16-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRB | Shifts an 8-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRD | Shifts a 32-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRQ | Shifts a 64-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRW | Shifts a 16-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KTESTB | Sets ZF if the AND of two 8-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KTESTD | Sets ZF if the AND of two 32-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KTESTQ | Sets ZF if the AND of two 64-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KTESTW | Sets ZF if the AND of two 16-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KUNPCKBW | Joins the low 8 bits of two masks into a 16-bit mask, the second source forming the low half. | AVX10.1 |
| KUNPCKDQ | Joins the low 32 bits of two masks into a 64-bit mask, the second source forming the low half. | AVX10.1 |
| KUNPCKWD | Joins the low 16 bits of two masks into a 32-bit mask, the second source forming the low half. | AVX10.1 |
| KXNORB | Computes the bitwise XNOR of two 8-bit masks. | AVX10.1 |
| KXNORD | Computes the bitwise XNOR of two 32-bit masks. | AVX10.1 |
| KXNORQ | Computes the bitwise XNOR of two 64-bit masks. | AVX10.1 |
| KXNORW | Computes the bitwise XNOR of two 16-bit masks. | AVX10.1 |
| KXORB | Computes the bitwise XOR of two 8-bit masks. | AVX10.1 |
| KXORD | Computes the bitwise XOR of two 32-bit masks. | AVX10.1 |
| KXORQ | Computes the bitwise XOR of two 64-bit masks. | AVX10.1 |
| KXORW | Computes the bitwise XOR of two 16-bit masks. | AVX10.1 |
| LAHF | Copies SF, ZF, AF, PF and CF into bits 7, 6, 4, 2 and 0 of AH; 64-bit mode needs the LAHF-SAHF feature. | LAHF-SAHF |
| LAR | Loads the access rights of the segment descriptor that a selector names and sets ZF, if the descriptor is visible at this privilege level. | System |
| LDDQU | Loads 128 unaligned bits into an XMM register like MOVDQU, but may read more bytes around them, for loads across cache lines; SSE3. | SSE3 |
| LDMXCSR | Loads the MXCSR register, the SSE control and status bits, from memory. | SSE |
| LDS | Loads a far pointer from memory into a register and DS; not in 64-bit mode, where its opcode C5 starts a VEX prefix. | General-purpose |
| LDTILECFG | Loads the AMX tile configuration (palette, rows and bytes per row of each tile) from a 64-byte memory block and zeroes the tile registers. | AMX-TILE, ACE, APX |
| LEA | Computes the address of a memory operand into a register without accessing memory, which compilers also use for arithmetic such as x*5+3. | General-purpose |
| LEAVE | Releases a stack frame: copies the frame pointer into the stack pointer, then pops the caller's frame pointer. | General-purpose |
| LES | Loads a far pointer from memory into a register and ES; not in 64-bit mode, where its opcode C4 starts a VEX prefix. | General-purpose |
| LFENCE | Waits until all earlier instructions have completed locally before any later one starts, which also bars speculative execution. | SSE2 |
| LFS | Loads a far pointer from memory into a register and FS. | General-purpose |
| LGDT | Loads the base and limit of the global descriptor table into GDTR from memory; ring 0 only. | System |
| LGS | Loads a far pointer from memory into a register and GS. | General-purpose |
| LIDT | Loads the base and limit of the interrupt descriptor table into IDTR from memory; ring 0 only. | System |
| LKGS | Loads GS from a selector but puts the descriptor's base in the IA32_KERNEL_GS_BASE MSR instead of the GS base; ring 0 of 64-bit mode only. | LKGS |
| LLDT | Loads the local descriptor table register from a selector of an LDT descriptor in the GDT; ring 0 only. | System |
| LLWPCB | Loads the address of a Lightweight Profiling control block from a register and starts profiling with it; LWP. | LWP |
| LMSW | Loads the low four bits of CR0 (PE, MP, EM and TS) from a word, the 80286's way into protected mode; ring 0 only. | System |
| LOADIWKEY | Loads the internal wrapping key of Key Locker from XMM registers; the key cannot be read back. Ring 0 only. | Key Locker |
| LODS | Loads the element at [RSI] into AL, AX, EAX or RAX and steps RSI up or down, as the direction flag says. | General-purpose |
| LOOP | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero. | General-purpose |
| LOOPE | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero and ZF is set. | General-purpose |
| LOOPNE | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero and ZF is clear. | General-purpose |
| LSL | Loads the limit of the segment descriptor that a selector names and sets ZF, if the descriptor is visible at this privilege level. | System |
| LSS | Loads a far pointer from memory into a register and SS, switching the stack segment and pointer with one instruction. | General-purpose |
| LTR | Loads the task register from a selector of a TSS descriptor in the GDT and marks that TSS busy; ring 0 only. | System |
| LWPINS | Inserts a record with a value of the program's choosing into the Lightweight Profiling ring buffer; LWP. | LWP |
| LWPVAL | Counts a programmed value sample event of Lightweight Profiling and records it when its counter runs out; LWP. | LWP |
| LZCNT | Counts the leading zero bits of an operand; APX adds a form that leaves the flags unchanged. | LZCNT, APX |
| MASKMOVDQU | Stores the bytes of an XMM register whose mask byte in a second register has its top bit set to [RDI], non-temporally. | SSE2 |
| MASKMOVQ | Stores the bytes of an MMX register whose mask byte in a second MMX register has its top bit set to [RDI], non-temporally; SSE. | SSE |
| MAXPD | Returns the larger of each pair of packed doubles, or the source element if either is NaN or both are zero. | SSE2 |
| MAXPS | Returns the larger of each pair of packed singles, or the source element if either is NaN or both are zero. | SSE |
| MAXSD | Returns the larger of the low doubles, or the source's if either is NaN or both are zero; the upper half is kept. | SSE2 |
| MAXSS | Returns the larger of the low singles, or the source's if either is NaN or both are zero; the other elements are kept. | SSE |
| MCOMMIT | Waits until earlier stores to memory with delayed error reporting have completed, and clears CF if any of them failed. | MCOMMIT |
| MFENCE | Makes all earlier loads and stores globally visible before any later load or store, a full memory barrier. | SSE2 |
| MINPD | Returns the smaller of each pair of packed doubles, or the source element if either is NaN or both are zero. | SSE2 |
| MINPS | Returns the smaller of each pair of packed singles, or the source element if either is NaN or both are zero. | SSE |
| MINSD | Returns the smaller of the low doubles, or the source's if either is NaN or both are zero; the upper half is kept. | SSE2 |
| MINSS | Returns the smaller of the low singles, or the source's if either is NaN or both are zero; the other elements are kept. | SSE |
| MONITOR | Arms the address monitor on the range holding the address in RAX, so that a later MWAIT waits for a store to it; ring 0 only. | MONITOR/MWAIT |
| MONITORX | Sets up the address range that MWAITX waits on, like MONITOR but usable at any privilege level. | MONITORX |
| MONTMUL | Performs a Montgomery multiplication in the PadLock Montgomery Multiplier, on operands that a block at [ESI] describes; VIA PadLock. | VIA PadLock |
| MOV | Copies data between registers, memory and immediates, and moves segment, control and debug registers; those last two only in ring 0. | General-purpose |
| MOVAPD | Moves packed doubles between XMM registers and memory, which must be aligned to 16 bytes. | SSE2 |
| MOVAPS | Moves packed singles between XMM registers and memory, which must be aligned to 16 bytes. | SSE |
| MOVBE | Loads or stores a 16-, 32- or 64-bit value with its byte order reversed; APX adds a register-to-register form. | MOVBE, APX |
| MOVD | Moves 32 bits between an MMX or XMM register and a general-purpose register or memory, zeroing the rest of a vector register. | SSE2, MMX |
| MOVDDUP | Loads or copies a double and duplicates it into both halves of an XMM register; SSE3. | SSE3 |
| MOVDIR64B | Copies 64 bytes from memory to a 64-byte-aligned destination as one direct store that is written atomically and bypasses the caches. | MOVDIR64B, APX |
| MOVDIRI | Stores a 32- or 64-bit register to memory as a direct store that bypasses the caches. | MOVDIRI, APX |
| MOVDQ2Q | Copies the low quadword of an XMM register to an MMX register. | SSE2 |
| MOVDQA | Moves 128 bits of integer data between XMM registers and memory, which must be aligned to 16 bytes. | SSE2 |
| MOVDQU | Moves 128 bits of integer data between XMM registers and memory without an alignment requirement. | SSE2 |
| MOVHLPS | Copies the high two singles of the source into the low half of the destination XMM register. | SSE |
| MOVHPD | Loads a double from memory into the high half of an XMM register, or stores the high double to memory. | SSE2 |
| MOVHPS | Loads two singles from memory into the high half of an XMM register, or stores the high two to memory. | SSE |
| MOVLHPS | Copies the low two singles of the source into the high half of the destination XMM register. | SSE |
| MOVLPD | Loads a double from memory into the low half of an XMM register, or stores the low double to memory. | SSE2 |
| MOVLPS | Loads two singles from memory into the low half of an XMM register, or stores the low two to memory. | SSE |
| MOVMSKPD | Copies the sign bits of two packed doubles into the low bits of a general-purpose register. | SSE2 |
| MOVMSKPS | Copies the sign bits of four packed singles into the low bits of a general-purpose register. | SSE |
| MOVNTDQ | Stores an XMM register to 16-byte aligned memory with a non-temporal hint that avoids polluting the caches. | SSE2 |
| MOVNTDQA | Loads 16 aligned bytes with a non-temporal hint, which lets it read write-combining memory efficiently; SSE4.1. | SSE4.1 |
| MOVNTI | Stores a general-purpose register to memory with a non-temporal hint that avoids polluting the caches; SSE2. | SSE2 |
| MOVNTPD | Stores packed doubles to 16-byte aligned memory with a non-temporal hint that avoids polluting the caches. | SSE2 |
| MOVNTPS | Stores packed singles to 16-byte aligned memory with a non-temporal hint that avoids polluting the caches. | SSE |
| MOVNTQ | Stores an MMX register to memory with a non-temporal hint, which lets the write bypass the caches; SSE. | SSE |
| MOVNTSD | Stores the low double of an XMM register to memory with a non-temporal hint; SSE4a. | SSE4a |
| MOVNTSS | Stores the low single of an XMM register to memory with a non-temporal hint; SSE4a. | SSE4a |
| MOVQ | Moves 64 bits between MMX or XMM registers, general-purpose registers and memory, zeroing the rest of an XMM destination. | SSE2, MMX |
| MOVQ2DQ | Copies an MMX register to the low quadword of an XMM register and zeroes the high quadword. | SSE2 |
| MOVRS | Loads a register from memory with a hint that other cores are likely to read the same data before it is written. | MOVRS, APX |
| MOVS | Copies the element at [RSI] to [RDI] and steps both pointers; REP MOVS copies RCX elements, the classic memcpy. | General-purpose |
| MOVSD | Moves the low double between XMM registers or to and from memory; a load zeroes the upper half, a register move keeps it. | SSE2 |
| MOVSHDUP | Duplicates each odd-numbered single into the even position below it; SSE3. | SSE3 |
| MOVSLDUP | Duplicates each even-numbered single into the odd position above it; SSE3. | SSE3 |
| MOVSS | Moves the low single between XMM registers or to and from memory; a load zeroes the rest, a register move keeps it. | SSE |
| MOVSX | Copies a signed byte or word into a wider register, extending its sign bit. | General-purpose |
| MOVSXD | Sign-extends a 32-bit register or memory operand into a 64-bit register (AT&T movslq); 64-bit mode only, where it took over ARPL's opcode. | General-purpose |
| MOVUPD | Moves packed doubles between XMM registers and memory without an alignment requirement. | SSE2 |
| MOVUPS | Moves packed singles between XMM registers and memory without an alignment requirement. | SSE |
| MOVZX | Copies an unsigned byte or word into a wider register, filling the upper bits with zeros. | General-purpose |
| MPSADBW | Computes eight word sums of absolute differences between a 4-byte block of the source and sliding blocks of the destination. | SSE4.1 |
| MUL | Multiplies unsigned integers, producing a double-width result in rDX:rAX (AX for bytes); APX adds a form that leaves the flags unchanged. | General-purpose, APX |
| MULPD | Multiplies the two packed doubles of the destination XMM register by those of the source. | SSE2 |
| MULPS | Multiplies the four packed singles of the destination XMM register by those of the source. | SSE |
| MULSD | Multiplies the low double of the destination by the low double of the source; the upper half is kept. | SSE2 |
| MULSS | Multiplies the low single of the destination by the low single of the source; the upper three elements are kept. | SSE |
| MULX | Multiplies rDX by an unsigned operand and writes the high and low halves of the product to two registers without touching the flags. | BMI2, APX |
| MWAIT | Waits in an optimized state that EAX hints at until the monitored range is written or an interrupt arrives; ring 0 only. | MONITOR/MWAIT |
| MWAITX | Waits until a store hits the range that MONITORX set up, or a timeout in EBX expires, at any privilege level. | MONITORX |
| NEG | Replaces an operand with its two's complement; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| NOP | Does nothing: 90 and the multi-byte 0F 1F forms pad code for alignment, and other opcodes of 0F 18 to 0F 1F are reserved to decode as NOPs. | General-purpose, PREFETCHW |
| NOT | Inverts every bit of an operand without changing the flags; APX adds a three-operand form. | General-purpose, APX |
| OR | Computes the bitwise OR of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ORPD | Computes the bitwise OR of two XMM operands, as packed doubles. | SSE2 |
| ORPS | Computes the bitwise OR of two XMM operands, as packed singles. | SSE |
| OUT | Writes AL, AX or EAX to an I/O port, given as an immediate or in DX, if IOPL or the TSS permission bitmap allows. | General-purpose |
| OUTS | Writes a byte, word or doubleword from memory at [RSI] to the I/O port in DX and steps RSI; REP repeats it RCX times. | General-purpose |
| PABSB | Computes the absolute values of packed signed bytes of an MMX or XMM operand; SSSE3. | SSSE3 |
| PABSD | Computes the absolute values of packed signed doublewords of an MMX or XMM operand; SSSE3. | SSSE3 |
| PABSW | Computes the absolute values of packed signed words of an MMX or XMM operand; SSSE3. | SSSE3 |
| PACKSSDW | Narrows signed doublewords of two MMX or XMM operands to words with signed saturation. | MMX, SSE2 |
| PACKSSWB | Narrows signed words of two MMX or XMM operands to bytes with signed saturation. | MMX, SSE2 |
| PACKUSDW | Narrows signed doublewords of two XMM operands to words with unsigned saturation; SSE4.1. | SSE4.1 |
| PACKUSWB | Narrows signed words of two MMX or XMM operands to bytes with unsigned saturation. | MMX, SSE2 |
| PADDB | Adds packed bytes of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PADDD | Adds packed doublewords of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PADDQ | Adds packed quadwords of MMX or XMM registers, wrapping around on overflow; SSE2. | SSE2 |
| PADDSB | Adds packed signed bytes of MMX or XMM registers with signed saturation. | MMX, SSE2 |
| PADDSW | Adds packed signed words of MMX or XMM registers with signed saturation. | MMX, SSE2 |
| PADDUSB | Adds packed unsigned bytes of MMX or XMM registers with unsigned saturation. | MMX, SSE2 |
| PADDUSW | Adds packed unsigned words of MMX or XMM registers with unsigned saturation. | MMX, SSE2 |
| PADDW | Adds packed words of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PALIGNR | Concatenates two MMX or XMM operands and extracts a register's worth of bytes at the byte offset an immediate gives; SSSE3. | SSSE3 |
| PAND | Computes the bitwise AND of two MMX or XMM operands. | MMX, SSE2 |
| PANDN | Computes the bitwise AND of the inverted destination with the source, in MMX or XMM registers. | MMX, SSE2 |
| PAUSE | Tells the processor it is in a spin-wait loop, which avoids a penalty on leaving the loop and saves power; a NOP before the Pentium 4. | General-purpose |
| PAVGB | Computes the rounded averages of packed unsigned bytes of MMX or XMM registers. | SSE, SSE2 |
| PAVGUSB | Computes the averages of packed unsigned bytes of two MMX operands, rounded up; 3DNow!. | 3DNow! |
| PAVGW | Computes the rounded averages of packed unsigned words of MMX or XMM registers. | SSE, SSE2 |
| PBLENDVB | Picks each byte from the destination or the source by the top bit of the matching byte of XMM0; SSE4.1. | SSE4.1 |
| PBLENDW | Picks each word from the destination or the source, as a bit of an immediate says; SSE4.1. | SSE4.1 |
| PBNDKB | Encrypts and authenticates a 256-byte bind structure with a platform key, for PCONFIG to use in configuring Total Storage Encryption. | PBNDKB |
| PCLMULQDQ | Carry-less multiplies one quadword of each operand, chosen by an immediate, into a 128-bit product. | PCLMULQDQ |
| PCMPEQB | Compares packed bytes of MMX or XMM registers for equality, into all-ones or all-zeros bytes. | MMX, SSE2 |
| PCMPEQD | Compares packed doublewords of MMX or XMM registers for equality, into all-ones or all-zeros elements. | MMX, SSE2 |
| PCMPEQQ | Compares packed quadwords for equality, into all-ones or all-zeros quadwords; SSE4.1. | SSE4.1 |
| PCMPEQW | Compares packed words of MMX or XMM registers for equality, into all-ones or all-zeros words. | MMX, SSE2 |
| PCMPESTRI | Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with REX.W) as an immediate says, returning an index in ECX. | SSE4.2 |
| PCMPESTRM | Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with REX.W) as an immediate says, returning a mask in XMM0. | SSE4.2 |
| PCMPGTB | Tests packed signed bytes of MMX or XMM registers for greater than, into all-ones or all-zeros bytes. | MMX, SSE2 |
| PCMPGTD | Tests packed signed doublewords of MMX or XMM registers for greater than, into all-ones or all-zeros elements. | MMX, SSE2 |
| PCMPGTQ | Tests packed signed quadwords for greater than, into all-ones or all-zeros quadwords; SSE4.2. | SSE4.2 |
| PCMPGTW | Tests packed signed words of MMX or XMM registers for greater than, into all-ones or all-zeros words. | MMX, SSE2 |
| PCMPISTRI | Compares two zero-terminated strings in XMM registers as an immediate says, returning an index in ECX; SSE4.2. | SSE4.2 |
| PCMPISTRM | Compares two zero-terminated strings in XMM registers as an immediate says, returning a bit or byte mask in XMM0. | SSE4.2 |
| PCONFIG | Configures platform features, such as the keys of multi-key memory encryption, with the leaf function in EAX; ring 0 only. | PCONFIG |
| PDEP | Deposits the low bits of the source at the bit positions selected by a mask, clearing the others. | BMI2, APX |
| PEXT | Extracts the bits of the source at the positions selected by a mask and packs them into the low bits of the destination. | BMI2, APX |
| PEXTRB | Copies the byte an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1. | SSE4.1 |
| PEXTRD | Copies the doubleword an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1. | SSE4.1 |
| PEXTRQ | Copies the quadword an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1. | SSE4.1 |
| PEXTRW | Copies the word an immediate selects from an MMX or XMM register to a general-purpose register, or to memory (SSE4.1). | SSE, SSE2, SSE4.1 |
| PF2ID | Converts two packed singles of an MMX register or memory to signed doublewords, saturating out-of-range values; 3DNow!. | 3DNow! |
| PF2IW | Converts two packed singles to signed words, saturated and sign-extended to doublewords; AMD's 3DNow! extensions. | 3DNow! |
| PFACC | Adds the two singles of each MMX operand, the first operand's sum going to the low half of the result; 3DNow!. | 3DNow! |
| PFADD | Adds the two packed singles of two MMX operands; 3DNow!. | 3DNow! |
| PFCMPEQ | Compares the packed singles of two MMX operands for equality, into all-ones or all-zeros doublewords; 3DNow!. | 3DNow! |
| PFCMPGE | Tests the packed singles of two MMX operands for greater than or equal, into all-ones or all-zeros doublewords; 3DNow!. | 3DNow! |
| PFCMPGT | Tests the packed singles of two MMX operands for greater than, into all-ones or all-zeros doublewords; 3DNow!. | 3DNow! |
| PFMAX | Returns the larger of each pair of packed singles of two MMX operands; 3DNow!. | 3DNow! |
| PFMIN | Returns the smaller of each pair of packed singles of two MMX operands; 3DNow!. | 3DNow! |
| PFMUL | Multiplies the two packed singles of two MMX operands; 3DNow!. | 3DNow! |
| PFNACC | Subtracts the high single from the low one within each MMX operand, the first operand's result going low; 3DNow! extensions. | 3DNow! |
| PFPNACC | Subtracts the high single from the low one of the first operand and adds the singles of the second; 3DNow! extensions. | 3DNow! |
| PFRCP | Approximates the reciprocal of the low single of an MMX register or memory, into both halves of the destination; 3DNow!. | 3DNow! |
| PFRCPIT1 | Performs the first Newton-Raphson step that refines a PFRCP reciprocal approximation; 3DNow!. | 3DNow! |
| PFRCPIT2 | Performs the second and last Newton-Raphson step that refines a PFRCP or PFRSQRT approximation; 3DNow!. | 3DNow! |
| PFRSQIT1 | Performs the first Newton-Raphson step that refines a PFRSQRT reciprocal square root approximation; 3DNow!. | 3DNow! |
| PFRSQRT | Approximates the reciprocal square root of the low single of an MMX register or memory, into both halves; 3DNow!. | 3DNow! |
| PFSUB | Subtracts the packed singles of the second MMX operand from those of the first; 3DNow!. | 3DNow! |
| PFSUBR | Subtracts the packed singles of the first MMX operand from those of the second, into the first; 3DNow!. | 3DNow! |
| PHADDD | Adds adjacent pairs of doublewords within each MMX or XMM operand, the destination's sums going low; SSSE3. | SSSE3 |
| PHADDSW | Adds adjacent pairs of signed words within each operand with signed saturation, the destination's sums going low; SSSE3. | SSSE3 |
| PHADDW | Adds adjacent pairs of words within each MMX or XMM operand, the destination's sums going low; SSSE3. | SSSE3 |
| PHMINPOSUW | Finds the smallest unsigned word of an XMM operand and returns it with its index in the low two words; SSE4.1. | SSE4.1 |
| PHSUBD | Subtracts the odd doubleword from the even one in adjacent pairs of each MMX or XMM operand; SSSE3. | SSSE3 |
| PHSUBSW | Subtracts the odd signed word from the even one in adjacent pairs of each operand with signed saturation; SSSE3. | SSSE3 |
| PHSUBW | Subtracts the odd word from the even one in adjacent pairs of each MMX or XMM operand; SSSE3. | SSSE3 |
| PI2FD | Converts two packed signed doublewords of an MMX register or memory to singles; 3DNow!. | 3DNow! |
| PI2FW | Converts the signed words in the low halves of two doublewords to packed singles; AMD's 3DNow! extensions. | 3DNow! |
| PINSRB | Inserts a byte from a general-purpose register or memory into an XMM register at the position an immediate gives; SSE4.1. | SSE4.1 |
| PINSRD | Inserts a doubleword from a general-purpose register or memory into an XMM register where an immediate says; SSE4.1. | SSE4.1 |
| PINSRQ | Inserts a quadword from a general-purpose register or memory into an XMM register where an immediate says; SSE4.1. | SSE4.1 |
| PINSRW | Inserts a word from a general-purpose register or memory into an MMX or XMM register at the position an immediate gives. | SSE, SSE2 |
| PMADDUBSW | Multiplies unsigned bytes of the destination by signed bytes of the source and adds adjacent products with signed saturation. | SSSE3 |
| PMADDWD | Multiplies packed signed words of MMX or XMM registers and adds adjacent products into doublewords. | MMX, SSE2 |
| PMAXSB | Returns the larger of each pair of signed bytes; SSE4.1. | SSE4.1 |
| PMAXSD | Returns the larger of each pair of signed doublewords; SSE4.1. | SSE4.1 |
| PMAXSW | Returns the larger of each pair of signed words of MMX or XMM registers. | SSE, SSE2 |
| PMAXUB | Returns the larger of each pair of unsigned bytes of MMX or XMM registers. | SSE, SSE2 |
| PMAXUD | Returns the larger of each pair of unsigned doublewords; SSE4.1. | SSE4.1 |
| PMAXUW | Returns the larger of each pair of unsigned words; SSE4.1. | SSE4.1 |
| PMINSB | Returns the smaller of each pair of signed bytes; SSE4.1. | SSE4.1 |
| PMINSD | Returns the smaller of each pair of signed doublewords; SSE4.1. | SSE4.1 |
| PMINSW | Returns the smaller of each pair of signed words of MMX or XMM registers. | SSE, SSE2 |
| PMINUB | Returns the smaller of each pair of unsigned bytes of MMX or XMM registers. | SSE, SSE2 |
| PMINUD | Returns the smaller of each pair of unsigned doublewords; SSE4.1. | SSE4.1 |
| PMINUW | Returns the smaller of each pair of unsigned words; SSE4.1. | SSE4.1 |
| PMOVMSKB | Copies the top bit of each byte of an MMX or XMM register into the low bits of a general-purpose register. | SSE, SSE2 |
| PMOVSXBD | Sign-extends the four low bytes of the source to doublewords; SSE4.1. | SSE4.1 |
| PMOVSXBQ | Sign-extends the two low bytes of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVSXBW | Sign-extends the eight low bytes of the source to words; SSE4.1. | SSE4.1 |
| PMOVSXDQ | Sign-extends the two low doublewords of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVSXWD | Sign-extends the four low words of the source to doublewords; SSE4.1. | SSE4.1 |
| PMOVSXWQ | Sign-extends the two low words of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVZXBD | Zero-extends the four low bytes of the source to doublewords; SSE4.1. | SSE4.1 |
| PMOVZXBQ | Zero-extends the two low bytes of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVZXBW | Zero-extends the eight low bytes of the source to words; SSE4.1. | SSE4.1 |
| PMOVZXDQ | Zero-extends the two low doublewords of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVZXWD | Zero-extends the four low words of the source to doublewords; SSE4.1. | SSE4.1 |
| PMOVZXWQ | Zero-extends the two low words of the source to quadwords; SSE4.1. | SSE4.1 |
| PMULDQ | Multiplies the signed low doubleword of each quadword into 64-bit products; SSE4.1. | SSE4.1 |
| PMULHRSW | Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result; SSSE3. | SSSE3 |
| PMULHRW | Multiplies packed signed words of two MMX operands and keeps the high 16 bits of each product, rounded; 3DNow!. | 3DNow! |
| PMULHUW | Multiplies packed unsigned words of MMX or XMM registers and keeps the high 16 bits of each product. | SSE, SSE2 |
| PMULHW | Multiplies packed signed words of MMX or XMM registers and keeps the high 16 bits of each product. | MMX, SSE2 |
| PMULLD | Multiplies packed doublewords and keeps the low 32 bits of each product; SSE4.1. | SSE4.1 |
| PMULLW | Multiplies packed words of MMX or XMM registers and keeps the low 16 bits of each product. | MMX, SSE2 |
| PMULUDQ | Multiplies the unsigned low doubleword of each quadword of MMX or XMM registers into 64-bit products; SSE2. | SSE2 |
| POP | Loads the value on top of the stack into a register, memory or a segment register and moves the stack pointer past it. | General-purpose |
| POP2 | APX instruction that pops two 64-bit registers from a 16-byte-aligned stack slot. | APX |
| POP2P | POP2 with APX's push-pop acceleration hint, marking it as the partner of a PUSH2P so the processor can forward the values without the memory round trip. | APX |
| POPA | Pops the eight general-purpose registers that PUSHA saved, 16-bit or with POPAD 32-bit, discarding the saved stack pointer; not in 64-bit mode. | General-purpose |
| POPCNT | Counts the bits that are set in an operand; APX adds a form that leaves the flags unchanged. | POPCNT, APX |
| POPF | Pops the flags from the stack, changing only those the privilege level allows; POPFQ, the 64-bit form, pops RFLAGS. | General-purpose |
| POPP | Pops a 64-bit register with APX's push-pop acceleration hint, marking it as the partner of an earlier PUSHP. | APX |
| POR | Computes the bitwise OR of two MMX or XMM operands. | MMX, SSE2 |
| PREFETCH | Loads the cache line of a byte in memory into the first-level data cache ahead of use; AMD lets reserved 0F 0D forms act the same. | PREFETCHW |
| PREFETCHIT0 | Prefetches code at a RIP-relative address into all cache levels; a no-op without RIP-relative addressing or on older processors. | PREFETCHI |
| PREFETCHIT1 | Prefetches code at a RIP-relative address into every cache level but L1; a no-op without RIP-relative addressing or on older processors. | PREFETCHI |
| PREFETCHNTA | Hints that the cache line holding a byte of memory should be fetched close to the processor while polluting the caches little. | SSE |
| PREFETCHRST2 | Prefetches data with a hint that several cores are likely to read it before it is written, into caches chosen for read sharing. | MOVRS |
| PREFETCHT0 | Hints that the cache line holding a byte of memory should be fetched into all levels of the cache hierarchy. | SSE |
| PREFETCHT1 | Hints that the cache line holding a byte of memory should be fetched into the second-level cache and higher. | SSE |
| PREFETCHT2 | Hints that the cache line holding a byte of memory should be fetched into the third-level cache and higher. | SSE |
| PREFETCHW | Loads the cache line of a byte in memory into the cache ahead of a write, in the modified state on AMD processors. | PREFETCHW |
| PREFETCHWT1 | Prefetches the cache line of a byte in memory into the second-level cache with intent to write, in exclusive state. | PREFETCHWT1 |
| PSADBW | Sums the absolute differences of unsigned bytes over each group of eight, into one 16-bit sum per quadword. | SSE, SSE2 |
| PSHUFB | Rearranges the bytes of an MMX or XMM register by an index byte per result, which zeroes the byte when its top bit is set; SSSE3. | SSSE3 |
| PSHUFD | Rearranges the four doublewords of an XMM operand as an immediate selects. | SSE2 |
| PSHUFHW | Rearranges the upper four words of an XMM operand as an immediate selects, copying the lower four. | SSE2 |
| PSHUFLW | Rearranges the lower four words of an XMM operand as an immediate selects, copying the upper four. | SSE2 |
| PSHUFW | Copies to an MMX register the words of another or of memory in the order four 2-bit fields of an immediate select; SSE. | SSE |
| PSIGNB | Negates, zeroes or keeps each signed byte of the destination as the matching source byte is negative, zero or positive; SSSE3. | SSSE3 |
| PSIGND | Negates, zeroes or keeps each doubleword of the destination as the matching source element is negative, zero or positive. | SSSE3 |
| PSIGNW | Negates, zeroes or keeps each signed word of the destination as the matching source word is negative, zero or positive; SSSE3. | SSSE3 |
| PSLLD | Shifts packed doublewords of an MMX or XMM register left by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSLLDQ | Shifts an XMM register left by the number of bytes an immediate gives, filling with zeros. | SSE2 |
| PSLLQ | Shifts packed quadwords of an MMX or XMM register left by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSLLW | Shifts packed words of an MMX or XMM register left by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSMASH | Splits the reverse map (RMP) entry of a 2-MByte page into the entries of its 512 4-KByte pages; SEV-SNP. | SEV-SNP |
| PSRAD | Shifts packed doublewords of an MMX or XMM register right arithmetically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSRAW | Shifts packed words of an MMX or XMM register right arithmetically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSRLD | Shifts packed doublewords of an MMX or XMM register right logically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSRLDQ | Shifts an XMM register right by the number of bytes an immediate gives, filling with zeros. | SSE2 |
| PSRLQ | Shifts packed quadwords of an MMX or XMM register right logically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSRLW | Shifts packed words of an MMX or XMM register right logically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSUBB | Subtracts packed bytes of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PSUBD | Subtracts packed doublewords of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PSUBQ | Subtracts packed quadwords of MMX or XMM registers, wrapping around on overflow; SSE2. | SSE2 |
| PSUBSB | Subtracts packed signed bytes of MMX or XMM registers with signed saturation. | MMX, SSE2 |
| PSUBSW | Subtracts packed signed words of MMX or XMM registers with signed saturation. | MMX, SSE2 |
| PSUBUSB | Subtracts packed unsigned bytes of MMX or XMM registers with unsigned saturation. | MMX, SSE2 |
| PSUBUSW | Subtracts packed unsigned words of MMX or XMM registers with unsigned saturation. | MMX, SSE2 |
| PSUBW | Subtracts packed words of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PSWAPD | Swaps the two doublewords of an MMX register or memory into another MMX register; AMD's 3DNow! extensions. | 3DNow! |
| PTEST | Sets ZF if the AND of two XMM operands is all zeros and CF if the AND of the inverted destination with the source is; SSE4.1. | SSE4.1 |
| PTWRITE | Writes a 32- or 64-bit value from a register or memory into the Intel Processor Trace stream, when tracing records such packets. | PTWRITE |
| PUNPCKHBW | Interleaves the high bytes of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKHDQ | Interleaves the high doublewords of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKHQDQ | Interleaves the high quadwords of two XMM operands. | SSE2 |
| PUNPCKHWD | Interleaves the high words of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKLBW | Interleaves the low bytes of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKLDQ | Interleaves the low doublewords of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKLQDQ | Interleaves the low quadwords of two XMM operands. | SSE2 |
| PUNPCKLWD | Interleaves the low words of two MMX or XMM operands. | MMX, SSE2 |
| PUSH | Moves the stack pointer down and stores a register, memory operand, immediate or segment register on top of the stack. | General-purpose |
| PUSH2 | APX instruction that pushes two 64-bit registers to a 16-byte-aligned stack slot. | APX |
| PUSH2P | PUSH2 with APX's push-pop acceleration hint, marking it as the partner of a POP2P so the processor can forward the values without the memory round trip. | APX |
| PUSHA | Pushes the eight 16-bit general-purpose registers, or with PUSHAD the 32-bit ones, including the original stack pointer; not in 64-bit mode. | General-purpose |
| PUSHF | Pushes the flags onto the stack: FLAGS, EFLAGS with PUSHFD, or RFLAGS with PUSHFQ, the default in 64-bit mode. | General-purpose |
| PUSHP | Pushes a 64-bit register with APX's push-pop acceleration hint, marking it as the partner of a later POPP. | APX |
| PVALIDATE | Lets an SEV-SNP guest validate a page of its memory, or take the validation back, in the reverse map (RMP). | SEV-SNP |
| PXOR | Computes the bitwise XOR of two MMX or XMM operands; with the same register twice it zeroes it. | MMX, SSE2 |
| RCL | Rotates an operand left through the carry flag; APX adds a three-operand form. | General-purpose, APX |
| RCPPS | Approximates the reciprocals of four packed singles, with a relative error of at most 1.5 times 2^-12. | SSE |
| RCPSS | Approximates the reciprocal of the low single, with a relative error of at most 1.5 times 2^-12; the other elements are kept. | SSE |
| RCR | Rotates an operand right through the carry flag; APX adds a three-operand form. | General-purpose, APX |
| RDFSBASE | Reads the FS base, where x86-64 Linux keeps a thread's TLS pointer, into a register; 64-bit mode, when the kernel set CR4.FSGSBASE. | FSGSBASE |
| RDGSBASE | Reads the GS base into a register; 64-bit mode, when the kernel set CR4.FSGSBASE. | FSGSBASE |
| RDMSR | Reads a model-specific register into EDX:EAX, or with MSR_IMM into any 64-bit register from an MSR number given as an immediate; allowed only in ring 0. | System, MSR_IMM, APX |
| RDMSRLIST | Reads up to 64 model-specific registers whose addresses are listed in a table in memory, selected by a bit mask in RCX, into a second table. | MSRLIST |
| RDPID | Reads the processor ID that the kernel stored in IA32_TSC_AUX (on Linux, the CPU and node number) without reading the time-stamp counter. | RDPID |
| RDPKRU | Reads PKRU, the access- and write-disable bits of the 16 protection keys, into EAX; ECX must be zero. | PKU |
| RDPMC | Reads the performance counter that ECX selects into EDX:EAX; user code may run it only where the kernel set CR4.PCE. | System |
| RDPRU | Reads the processor register that ECX selects, MPERF or APERF, into EDX:EAX, at any privilege level unless CR4.TSD is set. | RDPRU |
| RDRAND | Returns a random number from the processor's hardware generator; CF=1 means the value is valid, CF=0 that none was ready. | RDRAND |
| RDSEED | Returns a random number straight from the processor's entropy source, to seed other generators; CF=1 means the value is valid, CF=0 that none was ready. | RDSEED |
| RDSSPD | Copies the low 32 bits of the shadow-stack pointer into a register; a NOP where shadow stacks are off, which code can test for. | CET |
| RDSSPQ | Copies the 64-bit shadow-stack pointer into a register; a NOP where shadow stacks are off, which code can test for. | CET |
| RDTSC | Reads the time-stamp counter into EDX:EAX, unordered with nearby instructions; user code may run it unless CR4.TSD is set. | System |
| RDTSCP | Reads the time-stamp counter into EDX:EAX and IA32_TSC_AUX into ECX, once all earlier instructions have executed. | RDTSCP |
| RET | Returns from a procedure: pops the return address (and CS for a far return) and optionally releases stack bytes of the caller's arguments. | General-purpose |
| RMPADJUST | Changes the permissions of a guest page for a less privileged VMPL in the reverse map (RMP); SEV-SNP. | SEV-SNP |
| RMPUPDATE | Writes a new reverse map (RMP) entry for a page, which the hypervisor uses to assign it to a guest; SEV-SNP. | SEV-SNP |
| ROL | Rotates an operand left; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ROR | Rotates an operand right; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| RORX | Rotates the source right by an immediate count into a separate destination without touching the flags. | BMI2, APX |
| ROUNDPD | Rounds two packed doubles to integral values with the rounding mode of an immediate or MXCSR; SSE4.1. | SSE4.1 |
| ROUNDPS | Rounds four packed singles to integral values with the rounding mode of an immediate or MXCSR; SSE4.1. | SSE4.1 |
| ROUNDSD | Rounds the low double of the source to an integral value, by an immediate or MXCSR; the upper half is kept. | SSE4.1 |
| ROUNDSS | Rounds the low single of the source to an integral value, by an immediate or MXCSR; the other elements are kept. | SSE4.1 |
| RSM | Returns from system-management mode to the interrupted program and restores its state; valid only in SMM. | System |
| RSQRTPS | Approximates the reciprocal square roots of four packed singles, with a relative error of at most 1.5 times 2^-12. | SSE |
| RSQRTSS | Approximates the reciprocal square root of the low single to within 1.5 times 2^-12; the other elements are kept. | SSE |
| RSTORSSP | Switches the shadow-stack pointer to the one in a restore token in memory, the way user-space stack switching works under CET. | CET |
| SAHF | Stores bits 7, 6, 4, 2 and 0 of AH into SF, ZF, AF, PF and CF; 64-bit mode needs the LAHF-SAHF feature. | LAHF-SAHF |
| SALC | Sets AL to FFh if the carry flag is set and to 00h if not, like SBB AL, AL but without changing the flags; not in 64-bit mode. | General-purpose |
| SAR | Shifts an operand right, copying the sign bit into the vacated bits; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SARX | Shifts the source right arithmetically by a count in a register into a separate destination without touching the flags. | BMI2, APX |
| SAVEPREVSSP | Pushes a restore token onto the shadow stack that RSTORSSP switched away from, so it can be resumed later; CET. | CET |
| SBB | Subtracts an integer and the carry flag, the step that chains multi-word subtractions; APX adds a three-operand form. | General-purpose, APX |
| SCAS | Compares AL, AX, EAX or RAX with the element at [RDI], setting the flags as CMP would, and steps RDI; REPNE SCAS searches for a value. | General-purpose |
| SEAMCALL | Calls the SEAM module (the Intel TDX module) from a hypervisor in VMX root operation, entering SEAM root operation. | TDX |
| SEAMOPS | Invokes a SEAM-specific operation; only software in SEAM root operation, the SEAM module, can execute it. | TDX |
| SEAMRET | Returns from the SEAM module in SEAM root operation to the hypervisor that called it with SEAMCALL. | TDX |
| SENDUIPI | Sends a user interprocessor interrupt through the entry of the user-interrupt target table that a register selects. | UINTR |
| SERIALIZE | Waits until earlier instructions have completed and their stores are visible before fetching the next, without the side effects of CPUID. | SERIALIZE |
| SETcc | Writes 1 or 0 to a byte depending on a condition on the flags; APX adds a form that also clears the rest of the destination register. | General-purpose, APX |
| SETSSBSY | Marks the supervisor shadow-stack token at IA32_PL0_SSP busy and loads the shadow-stack pointer from it; not with FRED. | CET |
| SFENCE | Makes all earlier stores globally visible before any later store, which orders non-temporal and write-combining stores. | SSE |
| SGDT | Stores the base and limit of the global descriptor table to memory; user code may run it unless CR4.UMIP is set. | System |
| SHA1MSG1 | Performs the first step of the SHA-1 message schedule, an XOR of message dwords, for the next four. | SHA |
| SHA1MSG2 | Performs the second step of the SHA-1 message schedule, finishing four message dwords with a rotate. | SHA |
| SHA1NEXTE | Computes the SHA-1 state variable E after four rounds from the state and adds it to the next four message dwords. | SHA |
| SHA1RNDS4 | Performs four rounds of SHA-1, with the round function and constant chosen by an immediate. | SHA |
| SHA256MSG1 | Performs the first step of the SHA-256 message schedule for the next four message dwords. | SHA |
| SHA256MSG2 | Performs the second step of the SHA-256 message schedule, finishing four message dwords. | SHA |
| SHA256RNDS2 | Performs two rounds of SHA-256, taking the message words plus round constants from XMM0. | SHA |
| SHL | Shifts an operand left, filling with zeros (SAL is the same instruction); APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHLD | Shifts an operand left and fills the vacated bits from a second register; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHLX | Shifts the source left by a count in a register into a separate destination without touching the flags. | BMI2, APX |
| SHR | Shifts an operand right, filling with zeros; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHRD | Shifts an operand right and fills the vacated bits from a second register; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHRX | Shifts the source right logically by a count in a register into a separate destination without touching the flags. | BMI2, APX |
| SHUFPD | Picks one double from each operand for the two result positions, as an immediate selects. | SSE2 |
| SHUFPS | Picks two singles from the destination for the low half and two from the source for the high half, as an immediate selects. | SSE |
| SIDT | Stores the base and limit of the interrupt descriptor table to memory; user code may run it unless CR4.UMIP is set. | System |
| SKINIT | Reinitializes the processor securely and starts the secure loader at the physical address in EAX after measuring it; AMD SVM. | SVM |
| SLDT | Stores the selector in the local descriptor table register to a register or memory; CR4.UMIP keeps it from user code. | System |
| SLWPCB | Stores the Lightweight Profiling state to memory and returns the address of its control block in a register; LWP. | LWP |
| SMSW | Stores the machine status word, the low bits of CR0, to a register or memory; CR4.UMIP keeps it from user code. | System |
| SQRTPD | Computes the square roots of two packed doubles. | SSE2 |
| SQRTPS | Computes the square roots of four packed singles. | SSE |
| SQRTSD | Computes the square root of the low double of the source into the low double of the destination; the upper half is kept. | SSE2 |
| SQRTSS | Computes the square root of the low single of the source into the destination; the upper three elements are kept. | SSE |
| STAC | Sets the alignment-check flag (AC), which lets the kernel reach user pages despite SMAP until CLAC clears it; ring 0 only. | SMAP |
| STC | Sets the carry flag (CF). | General-purpose |
| STD | Sets the direction flag (DF), so that string instructions step downward through memory. | General-purpose |
| STGI | Sets the global interrupt flag (GIF) again, letting external interrupts through; AMD SVM. | SVM |
| STI | Sets the interrupt flag (IF), accepting maskable interrupts after the next instruction; where CPL is above IOPL it faults or sets the virtual one instead. | General-purpose |
| STMXCSR | Stores the MXCSR register, the SSE control and status bits, to memory. | SSE |
| STOS | Stores AL, AX, EAX or RAX at [RDI] and steps RDI; REP STOS fills RCX elements, the classic memset. | General-purpose |
| STR | Stores the selector in the task register to a register or memory; CR4.UMIP keeps it from user code. | System |
| STTILECFG | Stores the current AMX tile configuration to a 64-byte memory block. | AMX-TILE, ACE, APX |
| STUI | Sets the user interrupt flag (UIF), so that pending user interrupts can be delivered right after it. | UINTR |
| SUB | Subtracts one integer from another and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SUBPD | Subtracts the two packed doubles of the source from those of the destination XMM register. | SSE2 |
| SUBPS | Subtracts the four packed singles of the source from those of the destination XMM register. | SSE |
| SUBSD | Subtracts the low double of the source from the low double of the destination; the upper half is kept. | SSE2 |
| SUBSS | Subtracts the low single of the source from the low single of the destination; the upper three elements are kept. | SSE |
| SWAPGS | Exchanges the GS base with IA32_KERNEL_GS_BASE, so that a kernel entered by SYSCALL finds its per-CPU data; 64-bit mode, ring 0. | System |
| SYSCALL | Enters the kernel fast: saves RIP in RCX and RFLAGS in R11 and jumps to IA32_LSTAR at ring 0; the system call of 64-bit Linux. | SYSCALL/SYSRET |
| SYSENTER | Enters the kernel at the address and stack in the SYSENTER MSRs at ring 0, without saving a return point; used by 32-bit systems. | SYSENTER/SYSEXIT |
| SYSEXIT | Returns from a SYSENTER entry to ring 3 at the address in RDX or EDX, with the stack pointer in RCX or ECX; ring 0 only. | SYSENTER/SYSEXIT |
| SYSRET | Returns from SYSCALL to user mode, loading RIP from RCX and RFLAGS from R11; with REX.W to 64-bit code, without to 32-bit code. | SYSCALL/SYSRET |
| T1MSKC | Makes a mask of the trailing ones of the source, inverted (~x | (x + 1)); TBM. | TBM |
| TCMMIMFP16PS | Multiplies two tiles of complex half-precision numbers and accumulates the imaginary parts of the products into a single-precision tile. | AMX-COMPLEX |
| TCMMRLFP16PS | Multiplies two tiles of complex half-precision numbers and accumulates the real parts of the products into a single-precision tile. | AMX-COMPLEX |
| TCVTROWD2PS | Moves one row of a tile to a ZMM register, converting its 32-bit integers to single precision. | AMX-AVX512, ACE |
| TCVTROWPS2BF16H | Moves one row of a tile to a ZMM register, converting single precision to bfloat16 in the high half of each dword and zeroing the low half. | AMX-AVX512, ACE |
| TCVTROWPS2BF16L | Moves one row of a tile to a ZMM register, converting single precision to bfloat16 in the low half of each dword and zeroing the high half. | AMX-AVX512, ACE |
| TCVTROWPS2PHH | Moves one row of a tile to a ZMM register, converting single precision to half precision in the high half of each dword and zeroing the low half. | AMX-AVX512, ACE |
| TCVTROWPS2PHL | Moves one row of a tile to a ZMM register, converting single precision to half precision in the low half of each dword and zeroing the high half. | AMX-AVX512, ACE |
| TDCALL | Calls the SEAM module from a trust domain, a guest in SEAM non-root operation, by a VM exit. | TDX |
| TDPBF16PS | Multiplies two tiles of bfloat16 pairs and accumulates each row-by-column dot product into a single-precision tile. | AMX-BF16 |
| TDPBF8PS | Multiplies two tiles of E5M2 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TDPBHF8PS | Multiplies a tile of E5M2 FP8 values by a tile of E4M3 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TDPBSSD | Multiplies two tiles of signed bytes, four per dword, and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPBSUD | Multiplies a tile of signed bytes by a tile of unsigned bytes and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPBUSD | Multiplies a tile of unsigned bytes by a tile of signed bytes and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPBUUD | Multiplies two tiles of unsigned bytes, four per dword, and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPFP16PS | Multiplies two tiles of half-precision pairs and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP16 |
| TDPHBF8PS | Multiplies a tile of E4M3 FP8 values by a tile of E5M2 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TDPHF8PS | Multiplies two tiles of E4M3 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TEST | ANDs two operands to set SF, ZF and PF and clear CF and OF, discarding the result; TEST with the same register twice checks it for zero. | General-purpose |
| TESTUI | Copies the user interrupt flag (UIF) into CF. | UINTR |
| TILELOADD | Loads a tile from memory, row by row, with the row stride taken from the index register of its SIB-encoded address. | AMX-TILE, APX |
| TILELOADDRS | Loads a tile from memory like TILELOADD, with a hint that other cores are likely to read the same data before it is written. | AMX-MOVRS, APX |
| TILELOADDRST1 | Loads a tile like TILELOADDRS, with the added hint that the data will be reused but need not stay in the nearest cache. | AMX-MOVRS, APX |
| TILELOADDT1 | Loads a tile like TILELOADD, with a hint that the data will be reused but need not stay in the nearest cache. | AMX-TILE, APX |
| TILEMOVCOL | ACE instruction that writes a ZMM register into one column of a tile register, the column chosen by an immediate or a register. | ACE |
| TILEMOVROW | Moves one row of a tile register to a ZMM register, or with ACE also the other way, the row chosen by an immediate or a register. | AMX-AVX512, ACE |
| TILERELEASE | Returns the AMX tile configuration and all tile data to their initial state: unconfigured and zero. | AMX-TILE, ACE |
| TILESTORED | Stores a tile to memory, row by row, with the row stride taken from the index register of its SIB-encoded address. | AMX-TILE, APX |
| TILEZERO | Sets every byte of a tile register to zero. | AMX-TILE, ACE |
| TLBSYNC | Waits until every processor has carried out the INVLPGB invalidations that this processor sent. | INVLPGB |
| TOP2BF16PS | ACE rank-2 outer product: adds the dot product of each bfloat16 pair of one ZMM source with each pair of the other to a single-precision tile. | ACE |
| TOP4BSSD | ACE outer product of two ZMM registers of signed bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4BSUD | ACE outer product of a ZMM register of signed bytes with one of unsigned bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4BUSD | ACE outer product of a ZMM register of unsigned bytes with one of signed bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4BUUD | ACE outer product of two ZMM registers of unsigned bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4MXBF8PS | ACE outer product of E5M2 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TOP4MXBHF8PS | ACE outer product of E5M2 by E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TOP4MXBSSPS | ACE outer product of two ZMM registers of MX INT8 values, scaled by the block scale register and accumulated into a single-precision tile. | ACE |
| TOP4MXHBF8PS | ACE outer product of E4M3 by E5M2 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TOP4MXHF8PS | ACE outer product of E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TPAUSE | Waits in a light or deeper power-saving state, chosen by bit 0 of a register, until the time-stamp counter reaches EDX:EAX. | WAITPKG |
| TZCNT | Counts the trailing zero bits of an operand; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| TZMSK | Makes a mask of the trailing zeros of the source (~x & (x - 1)); TBM. | TBM |
| UCOMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | SSE2 |
| UCOMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | SSE |
| UD0 | Raises an invalid-opcode exception (#UD); some processors decode it without the ModR/M byte and operands that others read. | General-purpose |
| UD1 | Raises an invalid-opcode exception (#UD); its register and memory operands are decoded but not used. | General-purpose |
| UD2 | Raises an invalid-opcode exception (#UD); compilers emit it for __builtin_trap and code that must not be reached. | General-purpose |
| UDB | Raises an invalid-opcode exception (#UD) with the one-byte opcode D6, in 64-bit mode, where SALC is not available. | General-purpose |
| UIRET | Returns from a user-interrupt handler, popping the RIP, RFLAGS and RSP that delivery pushed, and sets UIF again. | UINTR |
| UMONITOR | Arms the address monitor on the range holding the address in a register, at any privilege level, for a later UMWAIT. | WAITPKG |
| UMWAIT | Waits in a light or deeper power-saving state until the UMONITOR range is written, an interrupt arrives or the TSC reaches EDX:EAX. | WAITPKG |
| UNPCKHPD | Interleaves the high doubles of two XMM operands. | SSE2 |
| UNPCKHPS | Interleaves the high two singles of two XMM operands. | SSE |
| UNPCKLPD | Interleaves the low doubles of two XMM operands. | SSE2 |
| UNPCKLPS | Interleaves the low two singles of two XMM operands. | SSE |
| URDMSR | Reads a model-specific register from user mode, if the operating system allows that register in its user-MSR bitmap. | USER_MSR, APX |
| UWRMSR | Writes a model-specific register from user mode, if the operating system allows that register in its user-MSR bitmap. | USER_MSR, APX |
| V4FMADDPS | Performs four fused multiply-adds of packed singles in a row, each with the next of four ZMM registers and the next single from memory. | AVX512_4FMAPS |
| V4FMADDSS | Performs four scalar fused multiply-adds of singles in a row, with the low singles of four consecutive registers and four from memory. | AVX512_4FMAPS |
| V4FNMADDPS | Performs four fused negated multiply-adds of packed singles in a row, with four consecutive ZMM registers and four singles from memory. | AVX512_4FMAPS |
| V4FNMADDSS | Performs four scalar fused negated multiply-adds of singles in a row, with four consecutive registers and four singles from memory. | AVX512_4FMAPS |
| VADDBF16 | Adds packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VADDPD | Adds packed doubles. | AVX, AVX10.1 |
| VADDPH | Adds packed half-precision values. | AVX10.1 |
| VADDPS | Adds packed singles. | AVX, AVX10.1 |
| VADDSD | Adds the low doubles; the other elements come from the first source. | AVX, AVX10.1 |
| VADDSH | Adds the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VADDSS | Adds the low singles; the other elements come from the first source. | AVX, AVX10.1 |
| VADDSUBPD | Subtracts in the even-numbered doubles and adds in the odd-numbered ones of two XMM or YMM sources, into a separate destination. | AVX |
| VADDSUBPS | Subtracts in the even-numbered singles and adds in the odd-numbered ones of two XMM or YMM sources, into a separate destination. | AVX |
| VAESDEC | Performs one round of AES decryption on each 128-bit lane with the round key of the matching lane. | AES-NI, VAES, AVX10.1 |
| VAESDECLAST | Performs the last round of AES decryption on each 128-bit lane with the round key of the matching lane. | AES-NI, VAES, AVX10.1 |
| VAESENC | Performs one round of AES encryption on each 128-bit lane with the round key of the matching lane. | AES-NI, VAES, AVX10.1 |
| VAESENCLAST | Performs the last round of AES encryption on each 128-bit lane with the round key of the matching lane. | AES-NI, VAES, AVX10.1 |
| VAESIMC | Applies InvMixColumns to an AES round key in an XMM register, the VEX form of AESIMC. | AES-NI |
| VAESKEYGENASSIST | Computes the substituted and rotated words, with a round constant from an immediate, that AES key expansion needs; VEX form. | AES-NI |
| VALIGND | Concatenates two vectors and extracts one vector's worth of doublewords starting at an element offset given by an immediate. | AVX10.1 |
| VALIGNQ | Concatenates two vectors and extracts one vector's worth of quadwords starting at an element offset given by an immediate. | AVX10.1 |
| VANDNPD | Computes the bitwise AND of the inverted first source with the second, as packed doubles. | AVX, AVX10.1 |
| VANDNPS | Computes the bitwise AND of the inverted first source with the second, as packed singles. | AVX, AVX10.1 |
| VANDPD | Computes the bitwise AND of packed doubles. | AVX, AVX10.1 |
| VANDPS | Computes the bitwise AND of packed singles. | AVX, AVX10.1 |
| VBCSTNEBF162PS | Loads one bfloat16 value from memory, converts it to single precision and broadcasts it to every element, without floating-point exceptions. | AVX-NE-CONVERT |
| VBCSTNESH2PS | Loads one half-precision value from memory, converts it to single precision and broadcasts it to every element, without floating-point exceptions. | AVX-NE-CONVERT |
| VBLENDMPD | Picks each of the packed doubles from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VBLENDMPS | Picks each of the packed singles from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VBLENDPD | Picks each double from the first or the second source, as a bit of an immediate says, into a separate XMM or YMM destination. | AVX |
| VBLENDPS | Picks each single from the first or the second source, as a bit of an immediate says, into a separate XMM or YMM destination. | AVX |
| VBLENDVPD | Picks each double from the first or the second source by the sign bit of the matching element of a fourth register operand. | AVX |
| VBLENDVPS | Picks each single from the first or the second source by the sign bit of the matching element of a fourth register operand. | AVX |
| VBROADCASTF128 | Loads 128 bits of floating-point data from memory into both halves of a YMM register. | AVX |
| VBROADCASTF32X2 | Copies a group of two singles (64 bits) from memory or a register to every such group of a vector. | AVX10.1 |
| VBROADCASTF32X4 | Copies a group of four singles (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTF32X8 | Copies a group of eight singles (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTF64X2 | Copies a group of two doubles (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTF64X4 | Copies a group of four doubles (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTI128 | Loads 128 bits of integer data from memory into both halves of a YMM register; AVX2. | AVX2 |
| VBROADCASTI32X2 | Copies a group of two doublewords (64 bits) from memory or a register to every such group of a vector. | AVX10.1 |
| VBROADCASTI32X4 | Copies a group of four doublewords (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTI32X8 | Copies a group of eight doublewords (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTI64X2 | Copies a group of two quadwords (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTI64X4 | Copies a group of four quadwords (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTSD | Copies one double from memory or an XMM register to every element of a vector. | AVX, AVX2, AVX10.1 |
| VBROADCASTSS | Copies one single from memory or an XMM register to every element of a vector. | AVX, AVX2, AVX10.1 |
| VCMPBF16 | Compares packed bfloat16 values with one of 32 predicates chosen by an immediate and writes the results to a mask register. | AVX10.2 |
| VCMPPD | Compares packed doubles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX10.1 |
| VCMPPH | Compares packed half-precision values with one of 32 predicates chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VCMPPS | Compares packed singles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX10.1 |
| VCMPSD | Compares the low doubles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX). | AVX, AVX10.1 |
| VCMPSH | Compares the low half-precision values with one of 32 predicates chosen by an immediate and writes the result to a mask register. | AVX10.1 |
| VCMPSS | Compares the low singles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX). | AVX, AVX10.1 |
| VCOMISBF16 | Compares the low bfloat16 values of two registers and sets ZF, PF and CF as COMISS does, without floating-point exceptions. | AVX10.2 |
| VCOMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception. | AVX, AVX10.1 |
| VCOMISH | Compares the low half-precision values and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception. | AVX10.1 |
| VCOMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception. | AVX, AVX10.1 |
| VCOMPRESSPD | Packs the doubles selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VCOMPRESSPS | Packs the singles selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VCOMXSD | Compares the low doubles and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation, unordered included; NaNs signal invalid. | AVX10.2 |
| VCOMXSH | Compares the low half-precision values and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation; NaNs signal invalid. | AVX10.2 |
| VCOMXSS | Compares the low singles and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation, unordered included; NaNs signal invalid. | AVX10.2 |
| VCVT2PH2BF8 | Converts two vectors of half-precision values into one vector of E5M2 FP8 values, rounding to nearest even. | AVX10.2 |
| VCVT2PH2BF8S | Converts two vectors of half-precision values into one vector of E5M2 FP8 values, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVT2PH2HF8 | Converts two vectors of half-precision values into one vector of E4M3 FP8 values, rounding to nearest even. | AVX10.2 |
| VCVT2PH2HF8S | Converts two vectors of half-precision values into one vector of E4M3 FP8 values, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVT2PS2PHX | Converts two vectors of single-precision values into one vector of half-precision values, rounding as MXCSR or the instruction selects. | AVX10.2 |
| VCVTBF162IBS | Converts packed bfloat16 values to signed bytes with saturation, rounding to nearest even, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTBF162IUBS | Converts packed bfloat16 values to saturated unsigned bytes, rounding to nearest even, each in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTBF42HF8 | Converts packed 4-bit E2M1 floating-point values to E4M3 FP8, which is exact. | AVX10_V2_AUX |
| VCVTBF62HF8 | Converts packed 6-bit E3M2 floating-point values to E4M3 FP8, which is exact. | AVX10_V2_AUX |
| VCVTBF82BF4S | Converts packed E5M2 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTBF82BF6S | Converts packed E5M2 FP8 values to the 6-bit E3M2 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTBF82PS | Converts packed E5M2 FP8 values to single precision, which is exact. | AVX10_V2_AUX |
| VCVTBIASPH2BF8 | Converts packed half-precision values to E5M2 FP8, adding an 8-bit bias below the kept bits before truncating, which allows stochastic rounding. | AVX10.2 |
| VCVTBIASPH2BF8S | Converts packed half-precision values to E5M2 FP8 with an 8-bit rounding bias, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTBIASPH2HF8 | Converts packed half-precision values to E4M3 FP8, adding an 8-bit bias below the kept bits before truncating, which allows stochastic rounding. | AVX10.2 |
| VCVTBIASPH2HF8S | Converts packed half-precision values to E4M3 FP8 with an 8-bit rounding bias, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTBIASPS2BF8 | Converts packed single-precision values to E5M2 FP8 with a rounding bias taken from another register, which allows stochastic rounding. | AVX10_V2_AUX |
| VCVTBIASPS2BF8S | Converts packed single-precision values to E5M2 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTBIASPS2HF8 | Converts packed single-precision values to E4M3 FP8 with a rounding bias taken from another register, which allows stochastic rounding. | AVX10_V2_AUX |
| VCVTBIASPS2HF8S | Converts packed single-precision values to E4M3 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTDQ2PD | Converts packed signed doublewords to doubles. | AVX, AVX10.1 |
| VCVTDQ2PH | Converts packed signed doublewords to half precision. | AVX10.1 |
| VCVTDQ2PS | Converts packed signed doublewords to singles. | AVX, AVX10.1 |
| VCVTHF62HF8 | Converts packed 6-bit E2M3 floating-point values to E4M3 FP8, which is exact. | AVX10_V2_AUX |
| VCVTHF82BF4S | Converts packed E4M3 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTHF82HF6S | Converts packed E4M3 FP8 values to the 6-bit E2M3 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTHF82PH | Converts packed E4M3 FP8 values to half precision, which is exact. | AVX10.2 |
| VCVTHF82PS | Converts packed E4M3 FP8 values to single precision, which is exact. | AVX10_V2_AUX |
| VCVTNE2PS2BF16 | Converts two vectors of singles into one vector of bfloat16 values, rounding to nearest even. | AVX10.1 |
| VCVTNEEBF162PS | Converts the even-numbered bfloat16 values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEEPH2PS | Converts the even-numbered half-precision values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEOBF162PS | Converts the odd-numbered bfloat16 values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEOPH2PS | Converts the odd-numbered half-precision values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEPS2BF16 | Converts packed single-precision values to bfloat16, rounding to nearest even with denormals flushed to zero and without consulting MXCSR. | AVX-NE-CONVERT, AVX10.1 |
| VCVTPD2DQ | Converts packed doubles to signed doublewords, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTPD2PH | Converts packed doubles to half precision, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2PS | Converts packed doubles to singles, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTPD2QQ | Converts packed doubles to signed quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2UDQ | Converts packed doubles to unsigned doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2UQQ | Converts packed doubles to unsigned quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2BF8 | Converts packed half-precision values to E5M2 FP8, rounding to nearest even. | AVX10.2 |
| VCVTPH2BF8S | Converts packed half-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTPH2DQ | Converts packed half-precision values to signed doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2HF8 | Converts packed half-precision values to E4M3 FP8, rounding to nearest even. | AVX10.2 |
| VCVTPH2HF8S | Converts packed half-precision values to E4M3 FP8, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTPH2IBS | Converts packed half-precision values to signed bytes with saturation, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTPH2IUBS | Converts packed half-precision values to unsigned bytes with saturation, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTPH2PD | Converts packed half-precision values to doubles, which is exact. | AVX10.1 |
| VCVTPH2PS | Converts packed half-precision values to singles, which is exact. | F16C, AVX10.1 |
| VCVTPH2PSX | Converts packed half-precision values to singles like VCVTPH2PS, in the AVX512-FP16 form that also takes a broadcast memory source. | AVX10.1 |
| VCVTPH2QQ | Converts packed half-precision values to signed quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2UDQ | Converts packed half-precision values to unsigned doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2UQQ | Converts packed half-precision values to unsigned quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2UW | Converts packed half-precision values to unsigned words, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2W | Converts packed half-precision values to signed words, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2BF8 | Converts packed single-precision values to E5M2 FP8, rounding to nearest even. | AVX10_V2_AUX |
| VCVTPS2BF8S | Converts packed single-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTPS2DQ | Converts packed singles to signed doublewords, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTPS2HF8 | Converts packed single-precision values to E4M3 FP8, rounding to nearest even. | AVX10_V2_AUX |
| VCVTPS2HF8S | Converts packed single-precision values to E4M3 FP8, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTPS2IBS | Converts packed single-precision values to signed bytes with saturation, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTPS2IUBS | Converts packed single-precision values to unsigned bytes with saturation, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTPS2PD | Converts packed singles to doubles, which is exact. | AVX, AVX10.1 |
| VCVTPS2PH | Converts packed singles to half precision, rounding as an immediate or MXCSR selects. | F16C, AVX10.1 |
| VCVTPS2PHX | Converts packed singles to half precision like VCVTPS2PH, but with a broadcast source and embedded rounding instead of an immediate. | AVX10.1 |
| VCVTPS2QQ | Converts packed singles to signed quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2UDQ | Converts packed singles to unsigned doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2UQQ | Converts packed singles to unsigned quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTQQ2PD | Converts packed signed quadwords to doubles. | AVX10.1 |
| VCVTQQ2PH | Converts packed signed quadwords to half precision. | AVX10.1 |
| VCVTQQ2PS | Converts packed signed quadwords to singles. | AVX10.1 |
| VCVTROPS2HF8 | Converts packed single-precision values to E4M3 FP8, rounding to odd, which avoids double-rounding errors when the result is narrowed again. | AVX10_V2_AUX |
| VCVTROPS2HF8S | Converts packed single-precision values to E4M3 FP8, rounding to odd and saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTSD2SH | Converts the low double of the second source to half precision, rounding as MXCSR or the instruction selects; the rest come from the first source. | AVX10.1 |
| VCVTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTSD2SS | Converts the low double of the second source to single, rounding as MXCSR or the instruction selects; the other elements come from the first source. | AVX, AVX10.1 |
| VCVTSD2USI | Converts the low double to an unsigned 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSH2SD | Converts the low half-precision value of the second source to double, which is exact; the other elements come from the first source. | AVX10.1 |
| VCVTSH2SI | Converts the low half-precision value to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSH2SS | Converts the low half-precision value of the second source to single, which is exact; the other elements come from the first source. | AVX10.1 |
| VCVTSH2USI | Converts the low half-precision value to an unsigned integer in a 32- or 64-bit register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSI2SD | Converts a signed 32- or 64-bit integer to double in the low element; the other elements come from the first source. | AVX, AVX10.1 |
| VCVTSI2SH | Converts a signed 32- or 64-bit integer to half precision in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTSI2SS | Converts a signed 32- or 64-bit integer to single in the low element; the other elements come from the first source. | AVX, AVX10.1 |
| VCVTSS2SD | Converts the low single of the second source to double, which is exact; the other elements come from the first source. | AVX, AVX10.1 |
| VCVTSS2SH | Converts the low single of the second source to half precision, rounding as MXCSR or the instruction selects; the rest come from the first source. | AVX10.1 |
| VCVTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTSS2USI | Converts the low single to an unsigned 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTTBF162IBS | Converts packed bfloat16 values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTBF162IUBS | Converts packed bfloat16 values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTPD2DQ | Converts packed doubles to signed doublewords, truncating toward zero. | AVX, AVX10.1 |
| VCVTTPD2DQS | Converts packed doubles to 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPD2QQ | Converts packed doubles to signed quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPD2QQS | Converts packed doubles to 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPD2UDQ | Converts packed doubles to unsigned doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPD2UDQS | Converts packed doubles to unsigned 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPD2UQQ | Converts packed doubles to unsigned quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPD2UQQS | Converts packed doubles to unsigned 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPH2DQ | Converts packed half-precision values to signed doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPH2IBS | Converts packed half-precision values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTPH2IUBS | Converts packed half-precision values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTPH2QQ | Converts packed half-precision values to signed quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPH2UDQ | Converts packed half-precision values to unsigned doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPH2UQQ | Converts packed half-precision values to unsigned quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPH2UW | Converts packed half-precision values to unsigned words, truncating toward zero. | AVX10.1 |
| VCVTTPH2W | Converts packed half-precision values to signed words, truncating toward zero. | AVX10.1 |
| VCVTTPS2DQ | Converts packed singles to signed doublewords, truncating toward zero. | AVX, AVX10.1 |
| VCVTTPS2DQS | Converts packed singles to 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPS2IBS | Converts packed single-precision values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTTPS2IUBS | Converts packed single-precision values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTTPS2QQ | Converts packed singles to signed quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPS2QQS | Converts packed singles to 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPS2UDQ | Converts packed singles to unsigned doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPS2UDQS | Converts packed singles to unsigned 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPS2UQQ | Converts packed singles to unsigned quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPS2UQQS | Converts packed singles to unsigned 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX, AVX10.1 |
| VCVTTSD2SIS | Converts the low double to a signed 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSD2USI | Converts the low double to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSD2USIS | Converts the low double to an unsigned 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSH2SI | Converts the low half-precision value to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSH2USI | Converts the low half-precision value to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX, AVX10.1 |
| VCVTTSS2SIS | Converts the low single to a signed 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSS2USI | Converts the low single to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSS2USIS | Converts the low single to an unsigned 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTUDQ2PD | Converts packed unsigned doublewords to doubles. | AVX10.1 |
| VCVTUDQ2PH | Converts packed unsigned doublewords to half precision. | AVX10.1 |
| VCVTUDQ2PS | Converts packed unsigned doublewords to singles. | AVX10.1 |
| VCVTUQQ2PD | Converts packed unsigned quadwords to doubles. | AVX10.1 |
| VCVTUQQ2PH | Converts packed unsigned quadwords to half precision. | AVX10.1 |
| VCVTUQQ2PS | Converts packed unsigned quadwords to singles. | AVX10.1 |
| VCVTUSI2SD | Converts an unsigned 32- or 64-bit integer to double in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTUSI2SH | Converts an unsigned 32- or 64-bit integer to half precision in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTUSI2SS | Converts an unsigned 32- or 64-bit integer to single in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTUW2PH | Converts packed unsigned words to half precision. | AVX10.1 |
| VCVTW2PH | Converts packed signed words to half precision. | AVX10.1 |
| VDBPSADBW | Sums absolute differences of 4-byte groups of the two sources into 16-bit results, after an immediate shuffles the second within each 128-bit lane. | AVX10.1 |
| VDIVBF16 | Divides packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VDIVPD | Divides packed doubles. | AVX, AVX10.1 |
| VDIVPH | Divides packed half-precision values. | AVX10.1 |
| VDIVPS | Divides packed singles. | AVX, AVX10.1 |
| VDIVSD | Divides the low doubles; the other elements come from the first source. | AVX, AVX10.1 |
| VDIVSH | Divides the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VDIVSS | Divides the low singles; the other elements come from the first source. | AVX, AVX10.1 |
| VDPBF16PS | Multiplies pairs of bfloat16 values and adds both products to the matching single-precision accumulator. | AVX10.1 |
| VDPPD | Computes a dot product of two packed doubles, with an immediate choosing which products to add and where the sum goes. | AVX |
| VDPPHPS | Multiplies pairs of half-precision values and adds both products to the matching single-precision accumulator. | AVX10.2 |
| VDPPS | Computes a dot product of the singles in each 128-bit lane, with an immediate choosing which products to add and where the sums go. | AVX |
| VERR | Sets ZF if the segment that a selector names can be read at this privilege level, without loading it. | System |
| VERW | Sets ZF if the segment that a selector names can be written at this privilege level, without loading it. | System |
| VEXP2PD | Approximates 2 to the power of each packed double of a ZMM register, with a relative error below 2^-23. | AVX512ER |
| VEXP2PS | Approximates 2 to the power of each packed single of a ZMM register, with a relative error below 2^-23. | AVX512ER |
| VEXPANDPD | Spreads consecutive doubles from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VEXPANDPS | Spreads consecutive singles from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VEXTRACTF128 | Copies the 128-bit half of a YMM register that an immediate selects to an XMM register or memory. | AVX |
| VEXTRACTF32X4 | Copies the 128-bit block of singles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTF32X8 | Copies the 256-bit block of singles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTF64X2 | Copies the 128-bit block of doubles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTF64X4 | Copies the 256-bit block of doubles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI128 | Copies the 128-bit half of a YMM register that an immediate selects to an XMM register or memory; AVX2. | AVX2 |
| VEXTRACTI32X4 | Copies the 128-bit block of doublewords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI32X8 | Copies the 256-bit block of doublewords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI64X2 | Copies the 128-bit block of quadwords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI64X4 | Copies the 256-bit block of quadwords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTPS | Copies the single that an immediate selects from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VFCMADDCPH | Multiplies packed complex half-precision numbers by the complex conjugates of the second source and adds the products to the destination. | AVX10.1 |
| VFCMADDCSH | Multiplies the low complex half-precision number of the first source by the conjugate of the second's and adds the product to the destination. | AVX10.1 |
| VFCMULCPH | Multiplies packed complex half-precision numbers by the complex conjugates of the second source. | AVX10.1 |
| VFCMULCSH | Multiplies the low complex half-precision number of the first source by the complex conjugate of the second source's. | AVX10.1 |
| VFIXUPIMMPD | Replaces special doubles (such as NaN) of the first source with responses from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFIXUPIMMPS | Replaces special singles (such as NaN) of the first source with responses from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFIXUPIMMSD | Replaces a special low double (such as NaN) of the first source with a response from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFIXUPIMMSS | Replaces a special low single (such as NaN) of the first source with a response from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFMADD132BF16 | Fused multiply-add of packed bfloat16 values: first operand times third plus second, into the first. | AVX10.2 |
| VFMADD132PD | Fused multiply-add of packed doubles: first operand times third plus second, into the first. | FMA, AVX10.1 |
| VFMADD132PH | Fused multiply-add of packed half-precision values: first operand times third plus second, into the first. | AVX10.1 |
| VFMADD132PS | Fused multiply-add of packed singles: first operand times third plus second, into the first. | FMA, AVX10.1 |
| VFMADD132SD | Fused multiply-add of the low doubles: first times third plus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD132SH | Fused multiply-add of the low half-precision values: first times third plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD132SS | Fused multiply-add of the low singles: first times third plus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD213BF16 | Fused multiply-add of packed bfloat16 values: second operand times first plus third, into the first. | AVX10.2 |
| VFMADD213PD | Fused multiply-add of packed doubles: second operand times first plus third, into the first. | FMA, AVX10.1 |
| VFMADD213PH | Fused multiply-add of packed half-precision values: second operand times first plus third, into the first. | AVX10.1 |
| VFMADD213PS | Fused multiply-add of packed singles: second operand times first plus third, into the first. | FMA, AVX10.1 |
| VFMADD213SD | Fused multiply-add of the low doubles: second times first plus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD213SH | Fused multiply-add of the low half-precision values: second times first plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD213SS | Fused multiply-add of the low singles: second times first plus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD231BF16 | Fused multiply-add of packed bfloat16 values: second operand times third plus first, into the first. | AVX10.2 |
| VFMADD231PD | Fused multiply-add of packed doubles: second operand times third plus first, into the first. | FMA, AVX10.1 |
| VFMADD231PH | Fused multiply-add of packed half-precision values: second operand times third plus first, into the first. | AVX10.1 |
| VFMADD231PS | Fused multiply-add of packed singles: second operand times third plus first, into the first. | FMA, AVX10.1 |
| VFMADD231SD | Fused multiply-add of the low doubles: second times third plus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD231SH | Fused multiply-add of the low half-precision values: second times third plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD231SS | Fused multiply-add of the low singles: second times third plus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADDCPH | Multiplies packed complex numbers, each a pair of half-precision values, and adds the products to the destination. | AVX10.1 |
| VFMADDCSH | Multiplies the low complex numbers, each a pair of half-precision values, and adds the product to the destination. | AVX10.1 |
| VFMADDPD | Multiplies packed doubles and adds a third operand, rounding once, with a separate destination (four operands); FMA4. | FMA4 |
| VFMADDPS | Multiplies packed singles and adds a third operand, rounding once, with a separate destination (four operands); FMA4. | FMA4 |
| VFMADDSD | Multiplies the low doubles of two operands and adds a third, rounding once, into a separate destination; FMA4. | FMA4 |
| VFMADDSS | Multiplies the low singles of two operands and adds a third, rounding once, into a separate destination; FMA4. | FMA4 |
| VFMADDSUB132PD | Fused multiply of packed doubles, first times third, minus the second in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB132PH | Fused multiply of packed half-precision values, first times third, minus the second in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB132PS | Fused multiply of packed singles, first times third, minus the second in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB213PD | Fused multiply of packed doubles, second times first, minus the third in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB213PH | Fused multiply of packed half-precision values, second times first, minus the third in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB213PS | Fused multiply of packed singles, second times first, minus the third in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB231PD | Fused multiply of packed doubles, second times third, minus the first in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB231PH | Fused multiply of packed half-precision values, second times third, minus the first in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB231PS | Fused multiply of packed singles, second times third, minus the first in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUBPD | Multiplies packed doubles and subtracts the third operand in even and adds it in odd elements, rounding once; FMA4. | FMA4 |
| VFMADDSUBPS | Multiplies packed singles and subtracts the third operand in even and adds it in odd elements, rounding once; FMA4. | FMA4 |
| VFMSUB132BF16 | Fused multiply-subtract of packed bfloat16 values: first operand times third minus second, into the first. | AVX10.2 |
| VFMSUB132PD | Fused multiply-subtract of packed doubles: first operand times third minus second, into the first. | FMA, AVX10.1 |
| VFMSUB132PH | Fused multiply-subtract of packed half-precision values: first operand times third minus second, into the first. | AVX10.1 |
| VFMSUB132PS | Fused multiply-subtract of packed singles: first operand times third minus second, into the first. | FMA, AVX10.1 |
| VFMSUB132SD | Fused multiply-subtract of the low doubles: first times third minus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB132SH | Fused multiply-subtract of the low half-precision values: first times third minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB132SS | Fused multiply-subtract of the low singles: first times third minus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB213BF16 | Fused multiply-subtract of packed bfloat16 values: second operand times first minus third, into the first. | AVX10.2 |
| VFMSUB213PD | Fused multiply-subtract of packed doubles: second operand times first minus third, into the first. | FMA, AVX10.1 |
| VFMSUB213PH | Fused multiply-subtract of packed half-precision values: second operand times first minus third, into the first. | AVX10.1 |
| VFMSUB213PS | Fused multiply-subtract of packed singles: second operand times first minus third, into the first. | FMA, AVX10.1 |
| VFMSUB213SD | Fused multiply-subtract of the low doubles: second times first minus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB213SH | Fused multiply-subtract of the low half-precision values: second times first minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB213SS | Fused multiply-subtract of the low singles: second times first minus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB231BF16 | Fused multiply-subtract of packed bfloat16 values: second operand times third minus first, into the first. | AVX10.2 |
| VFMSUB231PD | Fused multiply-subtract of packed doubles: second operand times third minus first, into the first. | FMA, AVX10.1 |
| VFMSUB231PH | Fused multiply-subtract of packed half-precision values: second operand times third minus first, into the first. | AVX10.1 |
| VFMSUB231PS | Fused multiply-subtract of packed singles: second operand times third minus first, into the first. | FMA, AVX10.1 |
| VFMSUB231SD | Fused multiply-subtract of the low doubles: second times third minus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB231SH | Fused multiply-subtract of the low half-precision values: second times third minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB231SS | Fused multiply-subtract of the low singles: second times third minus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUBADD132PD | Fused multiply of packed doubles, first times third, plus the second in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD132PH | Fused multiply of packed half-precision values, first times third, plus the second in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD132PS | Fused multiply of packed singles, first times third, plus the second in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD213PD | Fused multiply of packed doubles, second times first, plus the third in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD213PH | Fused multiply of packed half-precision values, second times first, plus the third in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD213PS | Fused multiply of packed singles, second times first, plus the third in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD231PD | Fused multiply of packed doubles, second times third, plus the first in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD231PH | Fused multiply of packed half-precision values, second times third, plus the first in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD231PS | Fused multiply of packed singles, second times third, plus the first in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADDPD | Multiplies packed doubles and adds the third operand in even and subtracts it in odd elements, rounding once; FMA4. | FMA4 |
| VFMSUBADDPS | Multiplies packed singles and adds the third operand in even and subtracts it in odd elements, rounding once; FMA4. | FMA4 |
| VFMSUBPD | Multiplies packed doubles and subtracts a third operand, rounding once, into a separate destination; FMA4. | FMA4 |
| VFMSUBPS | Multiplies packed singles and subtracts a third operand, rounding once, into a separate destination; FMA4. | FMA4 |
| VFMSUBSD | Multiplies the low doubles of two operands and subtracts a third, rounding once; FMA4. | FMA4 |
| VFMSUBSS | Multiplies the low singles of two operands and subtracts a third, rounding once; FMA4. | FMA4 |
| VFMULCPH | Multiplies packed complex numbers, each a pair of half-precision values. | AVX10.1 |
| VFMULCSH | Multiplies the low complex numbers, each a pair of half-precision values. | AVX10.1 |
| VFNMADD132BF16 | Fused negated multiply-add of packed bfloat16 values: minus first operand times third, plus second, into the first. | AVX10.2 |
| VFNMADD132PD | Fused negated multiply-add of packed doubles: minus first operand times third, plus second, into the first. | FMA, AVX10.1 |
| VFNMADD132PH | Fused negated multiply-add of packed half-precision values: minus first operand times third, plus second, into the first. | AVX10.1 |
| VFNMADD132PS | Fused negated multiply-add of packed singles: minus first operand times third, plus second, into the first. | FMA, AVX10.1 |
| VFNMADD132SD | Fused negated multiply-add of the low doubles: minus first times third, plus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD132SH | Fused negated multiply-add of the low half-precision values: minus first times third, plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD132SS | Fused negated multiply-add of the low singles: minus first times third, plus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD213BF16 | Fused negated multiply-add of packed bfloat16 values: minus second operand times first, plus third, into the first. | AVX10.2 |
| VFNMADD213PD | Fused negated multiply-add of packed doubles: minus second operand times first, plus third, into the first. | FMA, AVX10.1 |
| VFNMADD213PH | Fused negated multiply-add of packed half-precision values: minus second operand times first, plus third, into the first. | AVX10.1 |
| VFNMADD213PS | Fused negated multiply-add of packed singles: minus second operand times first, plus third, into the first. | FMA, AVX10.1 |
| VFNMADD213SD | Fused negated multiply-add of the low doubles: minus second times first, plus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD213SH | Fused negated multiply-add of the low half-precision values: minus second times first, plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD213SS | Fused negated multiply-add of the low singles: minus second times first, plus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD231BF16 | Fused negated multiply-add of packed bfloat16 values: minus second operand times third, plus first, into the first. | AVX10.2 |
| VFNMADD231PD | Fused negated multiply-add of packed doubles: minus second operand times third, plus first, into the first. | FMA, AVX10.1 |
| VFNMADD231PH | Fused negated multiply-add of packed half-precision values: minus second operand times third, plus first, into the first. | AVX10.1 |
| VFNMADD231PS | Fused negated multiply-add of packed singles: minus second operand times third, plus first, into the first. | FMA, AVX10.1 |
| VFNMADD231SD | Fused negated multiply-add of the low doubles: minus second times third, plus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD231SH | Fused negated multiply-add of the low half-precision values: minus second times third, plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD231SS | Fused negated multiply-add of the low singles: minus second times third, plus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADDPD | Negates the products of packed doubles and adds a third operand, rounding once; FMA4. | FMA4 |
| VFNMADDPS | Negates the products of packed singles and adds a third operand, rounding once; FMA4. | FMA4 |
| VFNMADDSD | Negates the product of the low doubles and adds a third operand, rounding once; FMA4. | FMA4 |
| VFNMADDSS | Negates the product of the low singles and adds a third operand, rounding once; FMA4. | FMA4 |
| VFNMSUB132BF16 | Fused negated multiply-subtract of packed bfloat16 values: minus first operand times third, minus second, into the first. | AVX10.2 |
| VFNMSUB132PD | Fused negated multiply-subtract of packed doubles: minus first operand times third, minus second, into the first. | FMA, AVX10.1 |
| VFNMSUB132PH | Fused negated multiply-subtract of packed half-precision values: minus first operand times third, minus second, into the first. | AVX10.1 |
| VFNMSUB132PS | Fused negated multiply-subtract of packed singles: minus first operand times third, minus second, into the first. | FMA, AVX10.1 |
| VFNMSUB132SD | Fused negated multiply-subtract of the low doubles: minus first times third, minus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB132SH | Fused negated multiply-subtract of the low half-precision values: minus first times third, minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB132SS | Fused negated multiply-subtract of the low singles: minus first times third, minus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB213BF16 | Fused negated multiply-subtract of packed bfloat16 values: minus second operand times first, minus third, into the first. | AVX10.2 |
| VFNMSUB213PD | Fused negated multiply-subtract of packed doubles: minus second operand times first, minus third, into the first. | FMA, AVX10.1 |
| VFNMSUB213PH | Fused negated multiply-subtract of packed half-precision values: minus second operand times first, minus third, into the first. | AVX10.1 |
| VFNMSUB213PS | Fused negated multiply-subtract of packed singles: minus second operand times first, minus third, into the first. | FMA, AVX10.1 |
| VFNMSUB213SD | Fused negated multiply-subtract of the low doubles: minus second times first, minus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB213SH | Fused negated multiply-subtract of the low half-precision values: minus second times first, minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB213SS | Fused negated multiply-subtract of the low singles: minus second times first, minus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB231BF16 | Fused negated multiply-subtract of packed bfloat16 values: minus second operand times third, minus first, into the first. | AVX10.2 |
| VFNMSUB231PD | Fused negated multiply-subtract of packed doubles: minus second operand times third, minus first, into the first. | FMA, AVX10.1 |
| VFNMSUB231PH | Fused negated multiply-subtract of packed half-precision values: minus second operand times third, minus first, into the first. | AVX10.1 |
| VFNMSUB231PS | Fused negated multiply-subtract of packed singles: minus second operand times third, minus first, into the first. | FMA, AVX10.1 |
| VFNMSUB231SD | Fused negated multiply-subtract of the low doubles: minus second times third, minus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB231SH | Fused negated multiply-subtract of the low half-precision values: minus second times third, minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB231SS | Fused negated multiply-subtract of the low singles: minus second times third, minus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUBPD | Negates the products of packed doubles and subtracts a third operand, rounding once; FMA4. | FMA4 |
| VFNMSUBPS | Negates the products of packed singles and subtracts a third operand, rounding once; FMA4. | FMA4 |
| VFNMSUBSD | Negates the product of the low doubles and subtracts a third operand, rounding once; FMA4. | FMA4 |
| VFNMSUBSS | Negates the product of the low singles and subtracts a third operand, rounding once; FMA4. | FMA4 |
| VFPCLASSBF16 | Tests packed bfloat16 values for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.2 |
| VFPCLASSPD | Tests packed doubles for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.1 |
| VFPCLASSPH | Tests packed half-precision values for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.1 |
| VFPCLASSPS | Tests packed singles for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.1 |
| VFPCLASSSD | Tests the low double for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register. | AVX10.1 |
| VFPCLASSSH | Tests the low half-precision value for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register. | AVX10.1 |
| VFPCLASSSS | Tests the low single for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register. | AVX10.1 |
| VFRCZPD | Extracts the fractional part of each packed double of an XMM or YMM operand, exactly; XOP. | XOP |
| VFRCZPS | Extracts the fractional part of each packed single of an XMM or YMM operand, exactly; XOP. | XOP |
| VFRCZSD | Extracts the fractional part of the low double of an XMM register or memory, exactly; XOP. | XOP |
| VFRCZSS | Extracts the fractional part of the low single of an XMM register or memory, exactly; XOP. | XOP |
| VGATHERDPD | Loads doubles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VGATHERDPS | Loads singles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VGATHERPF0DPD | Prefetches the doubles that a vector of doubleword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VGATHERPF0DPS | Prefetches the singles that a vector of doubleword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VGATHERPF0QPD | Prefetches the doubles that a vector of quadword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VGATHERPF0QPS | Prefetches the singles that a vector of quadword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VGATHERPF1DPD | Prefetches the doubles that a vector of doubleword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VGATHERPF1DPS | Prefetches the singles that a vector of doubleword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VGATHERPF1QPD | Prefetches the doubles that a vector of quadword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VGATHERPF1QPS | Prefetches the singles that a vector of quadword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VGATHERQPD | Loads doubles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VGATHERQPS | Loads singles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VGETEXPBF16 | Extracts the unbiased exponent of each packed bfloat16 value as a bfloat16 number. | AVX10.2 |
| VGETEXPPD | Extracts the unbiased exponent of packed doubles as floating-point numbers. | AVX10.1 |
| VGETEXPPH | Extracts the unbiased exponent of packed half-precision values as floating-point numbers. | AVX10.1 |
| VGETEXPPS | Extracts the unbiased exponent of packed singles as floating-point numbers. | AVX10.1 |
| VGETEXPSD | Extracts the unbiased exponent of the low double of the second source as a floating-point number; the other elements come from the first source. | AVX10.1 |
| VGETEXPSH | Extracts the unbiased exponent of the low half-precision value of the second source as a float; the other elements come from the first source. | AVX10.1 |
| VGETEXPSS | Extracts the unbiased exponent of the low single of the second source as a floating-point number; the other elements come from the first source. | AVX10.1 |
| VGETMANTBF16 | Extracts the normalized mantissa of each packed bfloat16 value, with the interval and sign handling chosen by an immediate. | AVX10.2 |
| VGETMANTPD | Extracts the normalized mantissa of packed doubles, with the interval and sign handling chosen by an immediate. | AVX10.1 |
| VGETMANTPH | Extracts the normalized mantissa of packed half-precision values, with the interval and sign handling chosen by an immediate. | AVX10.1 |
| VGETMANTPS | Extracts the normalized mantissa of packed singles, with the interval and sign handling chosen by an immediate. | AVX10.1 |
| VGETMANTSD | Extracts the normalized mantissa of the low double of the second source, as an immediate selects; the other elements come from the first source. | AVX10.1 |
| VGETMANTSH | Extracts the normalized mantissa of the low half-precision value of the second source, as an immediate selects; the rest come from the first source. | AVX10.1 |
| VGETMANTSS | Extracts the normalized mantissa of the low single of the second source, as an immediate selects; the other elements come from the first source. | AVX10.1 |
| VGF2P8AFFINEINVQB | Replaces each byte with its inverse in GF(2^8), then applies an affine transformation given by an 8x8 bit matrix and an immediate constant. | GFNI, AVX10.1 |
| VGF2P8AFFINEQB | Applies an affine transformation to each byte, given by an 8x8 bit matrix from the second source and an immediate constant. | GFNI, AVX10.1 |
| VGF2P8MULB | Multiplies bytes in the finite field GF(2^8) defined by the AES polynomial x^8 + x^4 + x^3 + x + 1. | GFNI, AVX10.1 |
| VHADDPD | Adds the pair of doubles within each 128-bit lane of two sources, the first source's sums going to the even positions. | AVX |
| VHADDPS | Adds adjacent pairs of singles within each 128-bit lane of two sources, the first source's two sums going low in the lane. | AVX |
| VHSUBPD | Subtracts the high double from the low one within each 128-bit lane of two sources, the first source's results going to the even positions. | AVX |
| VHSUBPS | Subtracts the odd single from the even one in adjacent pairs within each 128-bit lane, the first source's results going low. | AVX |
| VINSERTF128 | Copies the first source to a YMM register and replaces the half an immediate selects with 128 bits from an XMM register or memory. | AVX |
| VINSERTF32X4 | Replaces the 128-bit block that an immediate selects with four singles from a register or memory. | AVX10.1 |
| VINSERTF32X8 | Replaces the 256-bit block that an immediate selects with eight singles from a register or memory. | AVX10.1 |
| VINSERTF64X2 | Replaces the 128-bit block that an immediate selects with two doubles from a register or memory. | AVX10.1 |
| VINSERTF64X4 | Replaces the 256-bit block that an immediate selects with four doubles from a register or memory. | AVX10.1 |
| VINSERTI128 | Copies the first source to a YMM register and replaces the half an immediate selects with 128 bits of an XMM register or memory; AVX2. | AVX2 |
| VINSERTI32X4 | Replaces the 128-bit block that an immediate selects with four doublewords from a register or memory. | AVX10.1 |
| VINSERTI32X8 | Replaces the 256-bit block that an immediate selects with eight doublewords from a register or memory. | AVX10.1 |
| VINSERTI64X2 | Replaces the 128-bit block that an immediate selects with two quadwords from a register or memory. | AVX10.1 |
| VINSERTI64X4 | Replaces the 256-bit block that an immediate selects with four quadwords from a register or memory. | AVX10.1 |
| VINSERTPS | Inserts a single from a register or memory into an XMM register at the position an immediate gives, and can zero other elements. | AVX, AVX10.1 |
| VLDDQU | Loads 128 or 256 unaligned bits like VMOVDQU, but may read more bytes around them, for loads that cross cache lines. | AVX |
| VLDMXCSR | Loads the MXCSR register, the SSE control and status bits, from memory; the VEX form of LDMXCSR. | AVX |
| VMASKMOVDQU | Stores the bytes of an XMM register whose mask byte has its top bit set to [RDI], non-temporally; the VEX form of MASKMOVDQU. | AVX |
| VMASKMOVPD | Loads or stores packed doubles only where the sign bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault. | AVX |
| VMASKMOVPS | Loads or stores packed singles only where the sign bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault. | AVX |
| VMAXBF16 | Returns the larger of each pair of packed bfloat16 values, with the x86 convention of returning the second operand if either is NaN or both are zero. | AVX10.2 |
| VMAXPD | Returns the larger of each pair of packed doubles, or the second operand if either is NaN or both are zero. | AVX, AVX10.1 |
| VMAXPH | Returns the larger of each pair of packed half-precision values, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMAXPS | Returns the larger of each pair of packed singles, or the second operand if either is NaN or both are zero. | AVX, AVX10.1 |
| VMAXSD | Returns the larger of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX, AVX10.1 |
| VMAXSH | Returns the larger low half-precision value, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMAXSS | Returns the larger of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX, AVX10.1 |
| VMCALL | Causes a VM exit from a guest to its hypervisor, which defines what the call means. | VMX |
| VMCLEAR | Writes the data of the VMCS at a physical address back to its memory region and sets its launch state to clear. | VMX |
| VMFUNC | Invokes the VM function that EAX selects, such as EPTP switching (0), from a guest without a VM exit. | VMX |
| VMINBF16 | Returns the smaller of each pair of packed bfloat16 values, with the x86 convention of returning the second operand if either is NaN or both are zero. | AVX10.2 |
| VMINMAXBF16 | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed bfloat16 values, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXPD | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed doubles, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXPH | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed half-precision values, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXPS | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed singles, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXSD | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low doubles, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXSH | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low half-precision values, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXSS | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low singles, as an immediate selects, with sign control. | AVX10.2 |
| VMINPD | Returns the smaller of each pair of packed doubles, or the second operand if either is NaN or both are zero. | AVX, AVX10.1 |
| VMINPH | Returns the smaller of each pair of packed half-precision values, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMINPS | Returns the smaller of each pair of packed singles, or the second operand if either is NaN or both are zero. | AVX, AVX10.1 |
| VMINSD | Returns the smaller of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX, AVX10.1 |
| VMINSH | Returns the smaller low half-precision value, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMINSS | Returns the smaller of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX, AVX10.1 |
| VMLAUNCH | Enters the guest that the current VMCS describes, for a VMCS whose launch state is clear, and marks the VMCS launched. | VMX |
| VMLOAD | Loads the processor state that VMRUN does not load (segment and system registers) from the VMCB at the address in rAX; AMD SVM. | SVM |
| VMMCALL | Exits from a guest to its hypervisor with a VM exit, for a call whose meaning the hypervisor defines; AMD SVM. | SVM |
| VMOVAPD | Moves packed doubles between registers and memory that must be aligned to the vector size. | AVX, AVX10.1 |
| VMOVAPS | Moves packed singles between registers and memory that must be aligned to the vector size. | AVX, AVX10.1 |
| VMOVD | Moves 32 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form. | AVX, AVX10.1, AVX10.2 |
| VMOVDDUP | Duplicates each even-numbered double into the next odd position. | AVX, AVX10.1 |
| VMOVDQA | Moves 128 or 256 bits of integer data between vector registers and memory, which must be aligned to the vector size. | AVX |
| VMOVDQA32 | Moves integer vectors between registers and aligned memory, masked at doubleword granularity. | AVX10.1 |
| VMOVDQA64 | Moves integer vectors between registers and aligned memory, masked at quadword granularity. | AVX10.1 |
| VMOVDQU | Moves 128 or 256 bits of integer data between vector registers and memory without an alignment requirement. | AVX |
| VMOVDQU16 | Moves integer vectors between registers and memory without an alignment requirement, masked at word granularity. | AVX10.1 |
| VMOVDQU32 | Moves integer vectors between registers and memory without an alignment requirement, masked at doubleword granularity. | AVX10.1 |
| VMOVDQU64 | Moves integer vectors between registers and memory without an alignment requirement, masked at quadword granularity. | AVX10.1 |
| VMOVDQU8 | Moves integer vectors between registers and memory without an alignment requirement, masked at byte granularity. | AVX10.1 |
| VMOVHLPS | Moves the high two singles of the second source into the low half of the result, the high half coming from the first source. | AVX, AVX10.1 |
| VMOVHPD | Loads a double from memory into the high half of an XMM register, or stores the high double to memory. | AVX, AVX10.1 |
| VMOVHPS | Loads two singles from memory into the high half of an XMM register, or stores the high two to memory. | AVX, AVX10.1 |
| VMOVLHPS | Moves the low two singles of the second source into the high half of the result, the low half coming from the first source. | AVX, AVX10.1 |
| VMOVLPD | Loads a double from memory into the low half of an XMM register, or stores the low double to memory. | AVX, AVX10.1 |
| VMOVLPS | Loads two singles from memory into the low half of an XMM register, or stores the low two to memory. | AVX, AVX10.1 |
| VMOVMSKPD | Copies the sign bits of the packed doubles of an XMM or YMM register into the low bits of a general-purpose register. | AVX |
| VMOVMSKPS | Copies the sign bits of the packed singles of an XMM or YMM register into the low bits of a general-purpose register. | AVX |
| VMOVNTDQ | Stores an integer vector to aligned memory with a non-temporal hint that avoids polluting the caches. | AVX, AVX10.1 |
| VMOVNTDQA | Loads a vector from aligned memory with a non-temporal hint, which lets it read write-combining memory efficiently. | AVX, AVX2, AVX10.1 |
| VMOVNTPD | Stores packed doubles to aligned memory with a non-temporal hint that avoids polluting the caches. | AVX, AVX10.1 |
| VMOVNTPS | Stores packed singles to aligned memory with a non-temporal hint that avoids polluting the caches. | AVX, AVX10.1 |
| VMOVQ | Moves a quadword between an XMM register and a general-purpose register, memory or another XMM register, zeroing the rest of a vector destination. | AVX, AVX10.1 |
| VMOVRSB | Loads a vector of bytes under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVRSD | Loads a vector of doublewords under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVRSQ | Loads a vector of quadwords under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVRSW | Loads a vector of words under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVSD | Moves the low double between XMM registers or to and from memory; a load zeroes the rest of the register. | AVX, AVX10.1 |
| VMOVSH | Moves the low half-precision value between XMM registers or to and from memory; a load zeroes the rest of the register. | AVX10.1 |
| VMOVSHDUP | Duplicates each odd-numbered single into the even position below it. | AVX, AVX10.1 |
| VMOVSLDUP | Duplicates each even-numbered single into the odd position above it. | AVX, AVX10.1 |
| VMOVSS | Moves the low single between XMM registers or to and from memory; a load zeroes the rest of the register. | AVX, AVX10.1 |
| VMOVUPD | Moves packed doubles between registers and memory without an alignment requirement. | AVX, AVX10.1 |
| VMOVUPS | Moves packed singles between registers and memory without an alignment requirement. | AVX, AVX10.1 |
| VMOVW | Moves 16 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form. | AVX10.1, AVX10.2 |
| VMPSADBW | Computes, per 128-bit lane, word sums of absolute differences between a 4-byte block of the second source and eight sliding blocks of the first. | AVX, AVX2, AVX10.2 |
| VMPTRLD | Makes the VMCS at the physical address in a 64-bit memory operand the current VMCS. | VMX |
| VMPTRST | Stores the physical address of the current VMCS to a 64-bit memory operand. | VMX |
| VMREAD | Reads the field of the current VMCS whose encoding a register gives into a register or memory. | VMX |
| VMRESUME | Enters the guest that the current VMCS describes again, for a VMCS that VMLAUNCH has launched. | VMX |
| VMRUN | Runs the guest that the virtual machine control block (VMCB) at the physical address in rAX describes; AMD SVM. | SVM |
| VMSAVE | Saves the processor state that VMRUN does not save to the VMCB at the physical address in rAX; AMD SVM. | SVM |
| VMULBF16 | Multiplies packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VMULPD | Multiplies packed doubles. | AVX, AVX10.1 |
| VMULPH | Multiplies packed half-precision values. | AVX10.1 |
| VMULPS | Multiplies packed singles. | AVX, AVX10.1 |
| VMULSD | Multiplies the low doubles; the other elements come from the first source. | AVX, AVX10.1 |
| VMULSH | Multiplies the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VMULSS | Multiplies the low singles; the other elements come from the first source. | AVX, AVX10.1 |
| VMWRITE | Writes a register or memory operand to the field of the current VMCS whose encoding another register gives. | VMX |
| VMXOFF | Takes the processor out of VMX operation and unblocks INIT signals again. | VMX |
| VMXON | Puts the processor in VMX operation, taking the physical address of a 4-KByte VMXON region from a 64-bit memory operand. | VMX |
| VORPD | Computes the bitwise OR of packed doubles. | AVX, AVX10.1 |
| VORPS | Computes the bitwise OR of packed singles. | AVX, AVX10.1 |
| VP2INTERSECTD | Compares every doubleword of one vector with every one of another and marks the elements that have a match in a pair of mask registers. | AVX512-VP2INTERSECT |
| VP2INTERSECTQ | Compares every quadword of one vector with every one of another and marks the elements that have a match in a pair of mask registers. | AVX512-VP2INTERSECT |
| VP4DPWSSD | Adds four dot products of signed word pairs in a row to doublewords, with four consecutive ZMM registers and memory. | AVX512_4VNNIW |
| VP4DPWSSDS | Adds four dot products of signed word pairs in a row to doublewords with signed saturation, with four consecutive ZMM registers. | AVX512_4VNNIW |
| VPABSB | Computes the absolute value of packed signed bytes. | AVX, AVX2, AVX10.1 |
| VPABSD | Computes the absolute value of packed signed doublewords. | AVX, AVX2, AVX10.1 |
| VPABSQ | Computes the absolute value of packed signed quadwords. | AVX10.1 |
| VPABSW | Computes the absolute value of packed signed words. | AVX, AVX2, AVX10.1 |
| VPACKSSDW | Narrows signed doublewords from two sources to words with signed saturation. | AVX, AVX2, AVX10.1 |
| VPACKSSWB | Narrows signed words from two sources to bytes with signed saturation. | AVX, AVX2, AVX10.1 |
| VPACKUSDW | Narrows signed doublewords from two sources to words with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPACKUSWB | Narrows signed words from two sources to bytes with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPADDB | Adds packed bytes, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPADDD | Adds packed doublewords, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPADDQ | Adds packed quadwords, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPADDSB | Adds packed signed bytes with signed saturation. | AVX, AVX2, AVX10.1 |
| VPADDSW | Adds packed signed words with signed saturation. | AVX, AVX2, AVX10.1 |
| VPADDUSB | Adds packed unsigned bytes with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPADDUSW | Adds packed unsigned words with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPADDW | Adds packed words, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPALIGNR | Concatenates two sources in each 128-bit lane and extracts 16 bytes starting at a byte offset given by an immediate. | AVX, AVX2, AVX10.1 |
| VPAND | Computes the bitwise AND of two XMM or YMM sources into a separate destination (YMM with AVX2). | AVX, AVX2 |
| VPANDD | Computes the bitwise AND of two vectors, masked at doubleword granularity. | AVX10.1 |
| VPANDN | Computes the bitwise AND of the inverted first source with the second, in XMM or YMM registers (YMM with AVX2). | AVX, AVX2 |
| VPANDND | Computes the bitwise AND of the inverted first source with the second, masked at doubleword granularity. | AVX10.1 |
| VPANDNQ | Computes the bitwise AND of the inverted first source with the second, masked at quadword granularity. | AVX10.1 |
| VPANDQ | Computes the bitwise AND of two vectors, masked at quadword granularity. | AVX10.1 |
| VPAVGB | Computes the rounded average of packed unsigned bytes. | AVX, AVX2, AVX10.1 |
| VPAVGW | Computes the rounded average of packed unsigned words. | AVX, AVX2, AVX10.1 |
| VPBLENDD | Picks each doubleword from the first or the second source, as a bit of an immediate says; AVX2. | AVX2 |
| VPBLENDMB | Picks each byte from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDMD | Picks each doubleword from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDMQ | Picks each quadword from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDMW | Picks each word from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDVB | Picks each byte from the first or the second source by the top bit of the matching byte of a fourth register operand. | AVX, AVX2 |
| VPBLENDW | Picks each word from the first or the second source by a bit of an immediate, the same eight bits for each 128-bit lane. | AVX, AVX2 |
| VPBROADCASTB | Copies one byte from a register or memory to every byte of a vector. | AVX2, AVX10.1 |
| VPBROADCASTD | Copies one doubleword from a register or memory to every doubleword of a vector. | AVX2, AVX10.1 |
| VPBROADCASTMB2Q | Copies the low 8 bits of a mask register, zero-extended, to every quadword. | AVX10.1 |
| VPBROADCASTMW2D | Copies the low 16 bits of a mask register, zero-extended, to every doubleword. | AVX10.1 |
| VPBROADCASTQ | Copies one quadword from a register or memory to every quadword of a vector. | AVX2, AVX10.1 |
| VPBROADCASTW | Copies one word from a register or memory to every word of a vector. | AVX2, AVX10.1 |
| VPCLMULQDQ | Carry-less multiplies one quadword of each source, chosen by an immediate, into a 128-bit product in each 128-bit lane. | AVX, VPCLMULQDQ, AVX10.1 |
| VPCMOV | Takes each bit from the first or the second source as the matching bit of a third source is set or clear; XOP. | XOP |
| VPCMPB | Compares packed signed bytes with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPD | Compares packed signed doublewords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPEQB | Compares packed bytes for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPEQD | Compares packed doublewords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPEQQ | Compares packed quadwords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPEQW | Compares packed words for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPESTRI | Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with VEX.W1) as an immediate says, returning an index in ECX. | AVX |
| VPCMPESTRM | Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with VEX.W1) as an immediate says, returning a mask in XMM0. | AVX |
| VPCMPGTB | Tests packed signed bytes for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPGTD | Tests packed signed doublewords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPGTQ | Tests packed signed quadwords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPGTW | Tests packed signed words for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPISTRI | Compares two zero-terminated strings in XMM registers as an immediate says, returning an index in ECX; VEX form. | AVX |
| VPCMPISTRM | Compares two zero-terminated strings in XMM registers as an immediate says, returning a mask in XMM0; VEX form. | AVX |
| VPCMPQ | Compares packed signed quadwords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUB | Compares packed unsigned bytes with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUD | Compares packed unsigned doublewords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUQ | Compares packed unsigned quadwords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUW | Compares packed unsigned words with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPW | Compares packed signed words with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCOMB | Compares packed signed bytes by the predicate an immediate selects, such as less than (VPCOMLTB), into all-ones or all-zeros bytes; XOP. | XOP |
| VPCOMD | Compares packed signed doublewords by the predicate an immediate selects, into all-ones or all-zeros doublewords; XOP. | XOP |
| VPCOMPRESSB | Packs the bytes selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMPRESSD | Packs the doublewords selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMPRESSQ | Packs the quadwords selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMPRESSW | Packs the words selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMQ | Compares packed signed quadwords by the predicate an immediate selects, into all-ones or all-zeros quadwords; XOP. | XOP |
| VPCOMUB | Compares packed unsigned bytes by the predicate an immediate selects, into all-ones or all-zeros bytes; XOP. | XOP |
| VPCOMUD | Compares packed unsigned doublewords by the predicate an immediate selects, into all-ones or all-zeros doublewords; XOP. | XOP |
| VPCOMUQ | Compares packed unsigned quadwords by the predicate an immediate selects, into all-ones or all-zeros quadwords; XOP. | XOP |
| VPCOMUW | Compares packed unsigned words by the predicate an immediate selects, into all-ones or all-zeros words; XOP. | XOP |
| VPCOMW | Compares packed signed words by the predicate an immediate selects, into all-ones or all-zeros words; XOP. | XOP |
| VPCONFLICTD | For each doubleword, sets a bit for every lower-numbered element of the source that holds the same value. | AVX10.1 |
| VPCONFLICTQ | For each quadword, sets a bit for every lower-numbered element of the source that holds the same value. | AVX10.1 |
| VPDPBSSD | Multiplies signed bytes by signed bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBSSDS | Multiplies signed bytes by signed bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator with signed saturation. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBSUD | Multiplies signed bytes of the first source by unsigned bytes of the second and adds each group of four products to a 32-bit accumulator. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBSUDS | Multiplies signed bytes of the first source by unsigned bytes of the second and adds each group of four products to a 32-bit accumulator, saturating. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBUSD | Multiplies unsigned bytes of the first source by signed bytes of the second and adds each group of four products to a 32-bit accumulator. | AVX-VNNI, AVX10.1 |
| VPDPBUSDS | Multiplies unsigned bytes of the first source by signed bytes of the second and adds each group of four products to a 32-bit accumulator, saturating. | AVX-VNNI, AVX10.1 |
| VPDPBUUD | Multiplies unsigned bytes by unsigned bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBUUDS | Multiplies unsigned bytes by unsigned bytes and adds each group of four products to the matching 32-bit accumulator with unsigned saturation. | AVX-VNNI-INT8, AVX10.2 |
| VPDPWSSD | Multiplies pairs of signed words, adds both products to the matching 32-bit accumulator. | AVX-VNNI, AVX10.1 |
| VPDPWSSDS | Multiplies pairs of signed words and adds both products to the matching 32-bit accumulator with signed saturation. | AVX-VNNI, AVX10.1 |
| VPDPWSUD | Multiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWSUDS | Multiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator, saturating. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUSD | Multiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUSDS | Multiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator, saturating. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUUD | Multiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUUDS | Multiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator with unsigned saturation. | AVX-VNNI-INT16, AVX10.2 |
| VPERM2F128 | Builds each 128-bit half of a YMM result from either half of two sources, or zero, as an immediate selects. | AVX |
| VPERM2I128 | Builds each 128-bit half of a YMM result from either half of two integer sources, or zero, as an immediate selects; AVX2. | AVX2 |
| VPERMB | Rearranges the bytes of a vector across the whole register using an index vector. | AVX10.1 |
| VPERMD | Rearranges the doublewords of a vector across the whole register using an index vector. | AVX2, AVX10.1 |
| VPERMI2B | Selects bytes from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2D | Selects doublewords from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2PD | Selects doubles from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2PS | Selects singles from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2Q | Selects quadwords from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2W | Selects words from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMIL2PD | Picks each double from either of two sources, or zero, by selectors in a third source and an immediate; XOP. | XOP |
| VPERMIL2PS | Picks each single from either of two sources, or zero, by selectors in a third source and an immediate; XOP. | XOP |
| VPERMILPD | Rearranges doubles within each 128-bit lane, controlled by an immediate or by a vector. | AVX, AVX10.1 |
| VPERMILPS | Rearranges singles within each 128-bit lane, controlled by an immediate or by a vector. | AVX, AVX10.1 |
| VPERMPD | Rearranges doubles across the whole register, controlled by an immediate or by an index vector. | AVX2, AVX10.1 |
| VPERMPS | Rearranges singles across the whole register using an index vector. | AVX2, AVX10.1 |
| VPERMQ | Rearranges quadwords across the whole register, controlled by an immediate or by an index vector. | AVX2, AVX10.1 |
| VPERMT2B | Selects bytes from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2D | Selects doublewords from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2PD | Selects doubles from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2PS | Selects singles from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2Q | Selects quadwords from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2W | Selects words from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMW | Rearranges the words of a vector across the whole register using an index vector. | AVX10.1 |
| VPEXPANDB | Spreads consecutive bytes from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXPANDD | Spreads consecutive doublewords from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXPANDQ | Spreads consecutive quadwords from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXPANDW | Spreads consecutive words from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXTRB | Copies the byte selected by an immediate from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VPEXTRD | Copies the doubleword selected by an immediate from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VPEXTRQ | Copies the quadword selected by an immediate from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VPEXTRW | Copies the word selected by an immediate from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VPGATHERDD | Loads doublewords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VPGATHERDQ | Loads quadwords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VPGATHERQD | Loads doublewords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VPGATHERQQ | Loads quadwords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VPHADDBD | Adds each group of four signed bytes into a signed doubleword; XOP. | XOP |
| VPHADDBQ | Adds each group of eight signed bytes into a signed quadword; XOP. | XOP |
| VPHADDBW | Adds each pair of adjacent signed bytes into a signed word; XOP. | XOP |
| VPHADDD | Adds adjacent pairs of doublewords within each 128-bit lane of two sources, the first source's sums going low in the lane. | AVX, AVX2 |
| VPHADDDQ | Adds each pair of adjacent signed doublewords into a signed quadword; XOP. | XOP |
| VPHADDSW | Adds adjacent pairs of signed words within each 128-bit lane with signed saturation, the first source's sums going low. | AVX, AVX2 |
| VPHADDUBD | Adds each group of four unsigned bytes into a doubleword; XOP. | XOP |
| VPHADDUBQ | Adds each group of eight unsigned bytes into a quadword; XOP. | XOP |
| VPHADDUBW | Adds each pair of adjacent unsigned bytes into a word; XOP. | XOP |
| VPHADDUDQ | Adds each pair of adjacent unsigned doublewords into a quadword; XOP. | XOP |
| VPHADDUWD | Adds each pair of adjacent unsigned words into a doubleword; XOP. | XOP |
| VPHADDUWQ | Adds each group of four unsigned words into a quadword; XOP. | XOP |
| VPHADDW | Adds adjacent pairs of words within each 128-bit lane of two sources, the first source's sums going low in the lane. | AVX, AVX2 |
| VPHADDWD | Adds each pair of adjacent signed words into a signed doubleword; XOP. | XOP |
| VPHADDWQ | Adds each group of four signed words into a signed quadword; XOP. | XOP |
| VPHMINPOSUW | Finds the smallest unsigned word of an XMM operand and returns it with its index in the low two words; VEX form. | AVX |
| VPHSUBBW | Subtracts the high signed byte from the low one of each word, into signed words; XOP. | XOP |
| VPHSUBD | Subtracts the odd doubleword from the even one in adjacent pairs within each 128-bit lane of two sources. | AVX, AVX2 |
| VPHSUBDQ | Subtracts the high signed doubleword from the low one of each quadword, into signed quadwords; XOP. | XOP |
| VPHSUBSW | Subtracts the odd signed word from the even one in adjacent pairs within each 128-bit lane, with signed saturation. | AVX, AVX2 |
| VPHSUBW | Subtracts the odd word from the even one in adjacent pairs within each 128-bit lane of two sources. | AVX, AVX2 |
| VPHSUBWD | Subtracts the high signed word from the low one of each doubleword, into signed doublewords; XOP. | XOP |
| VPINSRB | Inserts a byte from a register or memory into an XMM register at the position an immediate gives. | AVX, AVX10.1 |
| VPINSRD | Inserts a doubleword from a register or memory into an XMM register at the position an immediate gives. | AVX, AVX10.1 |
| VPINSRQ | Inserts a quadword from a register or memory into an XMM register at the position an immediate gives. | AVX, AVX10.1 |
| VPINSRW | Inserts a word from a register or memory into an XMM register at the position an immediate gives. | AVX, AVX10.1 |
| VPLZCNTD | Counts the leading zero bits of each doubleword. | AVX10.1 |
| VPLZCNTQ | Counts the leading zero bits of each quadword. | AVX10.1 |
| VPMACSDD | Multiplies packed signed doublewords and adds a third source to the products, keeping the low 32 bits without saturation; XOP. | XOP |
| VPMACSDQH | Multiplies the odd signed doublewords of two sources into quadwords and adds the quadwords of a third source; XOP. | XOP |
| VPMACSDQL | Multiplies the even signed doublewords of two sources into quadwords and adds the quadwords of a third source; XOP. | XOP |
| VPMACSSDD | Multiplies packed signed doublewords and adds a third source to the products, with signed saturation to doublewords; XOP. | XOP |
| VPMACSSDQH | Multiplies the odd signed doublewords of two sources and adds a third source's quadwords, with signed saturation; XOP. | XOP |
| VPMACSSDQL | Multiplies the even signed doublewords of two sources and adds a third source's quadwords, with signed saturation; XOP. | XOP |
| VPMACSSWD | Multiplies the odd signed words of two sources and adds a third source's doublewords, with signed saturation; XOP. | XOP |
| VPMACSSWW | Multiplies packed signed words and adds a third source's words to the products, with signed saturation; XOP. | XOP |
| VPMACSWD | Multiplies the odd signed words of two sources and adds a third source's doublewords, without saturation; XOP. | XOP |
| VPMACSWW | Multiplies packed signed words and adds a third source's words to the products, keeping the low 16 bits; XOP. | XOP |
| VPMADCSSWD | Multiplies packed signed words, adds adjacent products and a third source's doublewords, with signed saturation; XOP. | XOP |
| VPMADCSWD | Multiplies packed signed words, adds adjacent products and a third source's doublewords, without saturation; XOP. | XOP |
| VPMADD52HUQ | Multiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the high 52 bits of each product to a 64-bit accumulator. | AVX-IFMA, AVX10.1 |
| VPMADD52LUQ | Multiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the low 52 bits of each product to a 64-bit accumulator. | AVX-IFMA, AVX10.1 |
| VPMADDUBSW | Multiplies unsigned bytes of the first source by signed bytes of the second and adds adjacent products into words with signed saturation. | AVX, AVX2, AVX10.1 |
| VPMADDWD | Multiplies signed words and adds adjacent products into doublewords. | AVX, AVX2, AVX10.1 |
| VPMASKMOVD | Loads or stores packed doublewords only where the top bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault. | AVX2 |
| VPMASKMOVQ | Loads or stores packed quadwords only where the top bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault. | AVX2 |
| VPMAXSB | Returns the larger of each pair of signed bytes. | AVX, AVX2, AVX10.1 |
| VPMAXSD | Returns the larger of each pair of signed doublewords. | AVX, AVX2, AVX10.1 |
| VPMAXSQ | Returns the larger of each pair of signed quadwords. | AVX10.1 |
| VPMAXSW | Returns the larger of each pair of signed words. | AVX, AVX2, AVX10.1 |
| VPMAXUB | Returns the larger of each pair of unsigned bytes. | AVX, AVX2, AVX10.1 |
| VPMAXUD | Returns the larger of each pair of unsigned doublewords. | AVX, AVX2, AVX10.1 |
| VPMAXUQ | Returns the larger of each pair of unsigned quadwords. | AVX10.1 |
| VPMAXUW | Returns the larger of each pair of unsigned words. | AVX, AVX2, AVX10.1 |
| VPMINSB | Returns the smaller of each pair of signed bytes. | AVX, AVX2, AVX10.1 |
| VPMINSD | Returns the smaller of each pair of signed doublewords. | AVX, AVX2, AVX10.1 |
| VPMINSQ | Returns the smaller of each pair of signed quadwords. | AVX10.1 |
| VPMINSW | Returns the smaller of each pair of signed words. | AVX, AVX2, AVX10.1 |
| VPMINUB | Returns the smaller of each pair of unsigned bytes. | AVX, AVX2, AVX10.1 |
| VPMINUD | Returns the smaller of each pair of unsigned doublewords. | AVX, AVX2, AVX10.1 |
| VPMINUQ | Returns the smaller of each pair of unsigned quadwords. | AVX10.1 |
| VPMINUW | Returns the smaller of each pair of unsigned words. | AVX, AVX2, AVX10.1 |
| VPMOVB2M | Sets each bit of a mask register from the sign bit of the corresponding byte. | AVX10.1 |
| VPMOVD2M | Sets each bit of a mask register from the sign bit of the corresponding doubleword. | AVX10.1 |
| VPMOVDB | Narrows packed doublewords to bytes by truncation. | AVX10.1 |
| VPMOVDW | Narrows packed doublewords to words by truncation. | AVX10.1 |
| VPMOVM2B | Sets each byte to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVM2D | Sets each doubleword to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVM2Q | Sets each quadword to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVM2W | Sets each word to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVMSKB | Copies the top bit of each byte of an XMM or YMM register into the low bits of a general-purpose register. | AVX, AVX2 |
| VPMOVQ2M | Sets each bit of a mask register from the sign bit of the corresponding quadword. | AVX10.1 |
| VPMOVQB | Narrows packed quadwords to bytes by truncation. | AVX10.1 |
| VPMOVQD | Narrows packed quadwords to doublewords by truncation. | AVX10.1 |
| VPMOVQW | Narrows packed quadwords to words by truncation. | AVX10.1 |
| VPMOVSDB | Narrows packed signed doublewords to bytes with signed saturation. | AVX10.1 |
| VPMOVSDW | Narrows packed signed doublewords to words with signed saturation. | AVX10.1 |
| VPMOVSQB | Narrows packed signed quadwords to bytes with signed saturation. | AVX10.1 |
| VPMOVSQD | Narrows packed signed quadwords to doublewords with signed saturation. | AVX10.1 |
| VPMOVSQW | Narrows packed signed quadwords to words with signed saturation. | AVX10.1 |
| VPMOVSSDB | Narrows packed signed doublewords to bytes with symmetric saturation, to the range -127 to 127. | AVX10_V2_AUX |
| VPMOVSWB | Narrows packed signed words to bytes with signed saturation. | AVX10.1 |
| VPMOVSXBD | Sign-extends packed bytes to doublewords. | AVX, AVX2, AVX10.1 |
| VPMOVSXBQ | Sign-extends packed bytes to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVSXBW | Sign-extends packed bytes to words. | AVX, AVX2, AVX10.1 |
| VPMOVSXDQ | Sign-extends packed doublewords to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVSXWD | Sign-extends packed words to doublewords. | AVX, AVX2, AVX10.1 |
| VPMOVSXWQ | Sign-extends packed words to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVUSDB | Narrows packed unsigned doublewords to bytes with unsigned saturation. | AVX10.1 |
| VPMOVUSDW | Narrows packed unsigned doublewords to words with unsigned saturation. | AVX10.1 |
| VPMOVUSQB | Narrows packed unsigned quadwords to bytes with unsigned saturation. | AVX10.1 |
| VPMOVUSQD | Narrows packed unsigned quadwords to doublewords with unsigned saturation. | AVX10.1 |
| VPMOVUSQW | Narrows packed unsigned quadwords to words with unsigned saturation. | AVX10.1 |
| VPMOVUSWB | Narrows packed unsigned words to bytes with unsigned saturation. | AVX10.1 |
| VPMOVW2M | Sets each bit of a mask register from the sign bit of the corresponding word. | AVX10.1 |
| VPMOVWB | Narrows packed words to bytes by truncation. | AVX10.1 |
| VPMOVZXBD | Zero-extends packed bytes to doublewords. | AVX, AVX2, AVX10.1 |
| VPMOVZXBQ | Zero-extends packed bytes to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVZXBW | Zero-extends packed bytes to words. | AVX, AVX2, AVX10.1 |
| VPMOVZXDQ | Zero-extends packed doublewords to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVZXWD | Zero-extends packed words to doublewords. | AVX, AVX2, AVX10.1 |
| VPMOVZXWQ | Zero-extends packed words to quadwords. | AVX, AVX2, AVX10.1 |
| VPMULDQ | Multiplies the signed low doublewords of each quadword into 64-bit products. | AVX, AVX2, AVX10.1 |
| VPMULHRSW | Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result. | AVX, AVX2, AVX10.1 |
| VPMULHUW | Multiplies unsigned words and keeps the high 16 bits of each product. | AVX, AVX2, AVX10.1 |
| VPMULHW | Multiplies signed words and keeps the high 16 bits of each product. | AVX, AVX2, AVX10.1 |
| VPMULLD | Multiplies packed doublewords and keeps the low 32 bits of each product. | AVX, AVX2, AVX10.1 |
| VPMULLQ | Multiplies packed quadwords and keeps the low 64 bits of each product. | AVX10.1 |
| VPMULLW | Multiplies packed words and keeps the low 16 bits of each product. | AVX, AVX2, AVX10.1 |
| VPMULTISHIFTQB | For each byte of the result, takes 8 bits from the matching quadword of the second source at a bit offset given by a control byte of the first. | AVX10.1 |
| VPMULUDQ | Multiplies the unsigned low doublewords of each quadword into 64-bit products. | AVX, AVX2, AVX10.1 |
| VPOPCNTB | Counts the set bits in each byte. | AVX10.1 |
| VPOPCNTD | Counts the set bits in each doubleword. | AVX10.1 |
| VPOPCNTQ | Counts the set bits in each quadword. | AVX10.1 |
| VPOPCNTW | Counts the set bits in each word. | AVX10.1 |
| VPOR | Computes the bitwise OR of two XMM or YMM sources into a separate destination (YMM with AVX2). | AVX, AVX2 |
| VPORD | Computes the bitwise OR of two vectors, masked at doubleword granularity. | AVX10.1 |
| VPORQ | Computes the bitwise OR of two vectors, masked at quadword granularity. | AVX10.1 |
| VPPERM | Picks each byte of the result from 32 bytes of two sources and optionally inverts, reverses or replaces it, by selectors in a third; XOP. | XOP |
| VPROLD | Rotates each doubleword left by an immediate count. | AVX10.1 |
| VPROLQ | Rotates each quadword left by an immediate count. | AVX10.1 |
| VPROLVD | Rotates each doubleword left by the count in the matching element of the second source. | AVX10.1 |
| VPROLVQ | Rotates each quadword left by the count in the matching element of the second source. | AVX10.1 |
| VPRORD | Rotates each doubleword right by an immediate count. | AVX10.1 |
| VPRORQ | Rotates each quadword right by an immediate count. | AVX10.1 |
| VPRORVD | Rotates each doubleword right by the count in the matching element of the second source. | AVX10.1 |
| VPRORVQ | Rotates each quadword right by the count in the matching element of the second source. | AVX10.1 |
| VPROTB | Rotates each byte left or right by a signed count from an immediate or the matching byte of a register or memory; XOP. | XOP |
| VPROTD | Rotates each doubleword left or right by a signed count from an immediate or a register or memory; XOP. | XOP |
| VPROTQ | Rotates each quadword left or right by a signed count from an immediate or a register or memory; XOP. | XOP |
| VPROTW | Rotates each word left or right by a signed count from an immediate or a register or memory; XOP. | XOP |
| VPSADBW | Sums the absolute differences of unsigned bytes over each group of eight, giving one 16-bit sum per quadword. | AVX, AVX2, AVX10.1 |
| VPSCATTERDD | Stores doublewords to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSCATTERDQ | Stores quadwords to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSCATTERQD | Stores doublewords to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSCATTERQQ | Stores quadwords to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSHAB | Shifts each signed byte arithmetically left or right by the signed count in the matching byte of a second source; XOP. | XOP |
| VPSHAD | Shifts each signed doubleword arithmetically left or right by a signed count per element; XOP. | XOP |
| VPSHAQ | Shifts each signed quadword arithmetically left or right by a signed count per element; XOP. | XOP |
| VPSHAW | Shifts each signed word arithmetically left or right by a signed count per element; XOP. | XOP |
| VPSHLB | Shifts each byte logically left or right by the signed count in the matching byte of a second source; XOP. | XOP |
| VPSHLD | Shifts each doubleword logically left or right by a signed count per element; XOP. | XOP |
| VPSHLDD | Joins each doubleword of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half. | AVX10.1 |
| VPSHLDQ | Joins each quadword of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half. | AVX10.1 |
| VPSHLDVD | Joins each doubleword of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half. | AVX10.1 |
| VPSHLDVQ | Joins each quadword of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half. | AVX10.1 |
| VPSHLDVW | Joins each word of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half. | AVX10.1 |
| VPSHLDW | Joins each word of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half. | AVX10.1 |
| VPSHLQ | Shifts each quadword logically left or right by a signed count per element; XOP. | XOP |
| VPSHLW | Shifts each word logically left or right by a signed count per element; XOP. | XOP |
| VPSHRDD | Joins each doubleword of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half. | AVX10.1 |
| VPSHRDQ | Joins each quadword of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half. | AVX10.1 |
| VPSHRDVD | Joins each doubleword of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half. | AVX10.1 |
| VPSHRDVQ | Joins each quadword of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half. | AVX10.1 |
| VPSHRDVW | Joins each word of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half. | AVX10.1 |
| VPSHRDW | Joins each word of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half. | AVX10.1 |
| VPSHUFB | Rearranges bytes within each 128-bit lane using an index byte per result, which zeroes the byte when its top bit is set. | AVX, AVX2, AVX10.1 |
| VPSHUFBITQMB | Selects, for each byte of the second source, one bit of the matching quadword of the first and writes the bits to a mask register. | AVX10.1 |
| VPSHUFD | Rearranges doublewords within each 128-bit lane as an immediate selects. | AVX, AVX2, AVX10.1 |
| VPSHUFHW | Rearranges the upper four words of each 128-bit lane as an immediate selects. | AVX, AVX2, AVX10.1 |
| VPSHUFLW | Rearranges the lower four words of each 128-bit lane as an immediate selects. | AVX, AVX2, AVX10.1 |
| VPSIGNB | Negates, zeroes or keeps each signed byte of the first source as the matching byte of the second is negative, zero or positive. | AVX, AVX2 |
| VPSIGND | Negates, zeroes or keeps each doubleword of the first source as the matching one of the second is negative, zero or positive. | AVX, AVX2 |
| VPSIGNW | Negates, zeroes or keeps each signed word of the first source as the matching word of the second is negative, zero or positive. | AVX, AVX2 |
| VPSLLD | Shifts doublewords left by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSLLDQ | Shifts each 128-bit lane left by a number of bytes given by an immediate. | AVX, AVX2, AVX10.1 |
| VPSLLQ | Shifts quadwords left by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSLLVD | Shifts each doubleword left by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSLLVQ | Shifts each quadword left by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSLLVW | Shifts each word left by the count in the matching element of the second source. | AVX10.1 |
| VPSLLW | Shifts words left by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRAD | Shifts doublewords right arithmetically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRAQ | Shifts quadwords right arithmetically by one count from a register or an immediate. | AVX10.1 |
| VPSRAVD | Shifts each doubleword right arithmetically by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSRAVQ | Shifts each quadword right arithmetically by the count in the matching element of the second source. | AVX10.1 |
| VPSRAVW | Shifts each word right arithmetically by the count in the matching element of the second source. | AVX10.1 |
| VPSRAW | Shifts words right arithmetically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRLD | Shifts doublewords right logically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRLDQ | Shifts each 128-bit lane right by a number of bytes given by an immediate. | AVX, AVX2, AVX10.1 |
| VPSRLQ | Shifts quadwords right logically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRLVD | Shifts each doubleword right logically by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSRLVQ | Shifts each quadword right logically by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSRLVW | Shifts each word right logically by the count in the matching element of the second source. | AVX10.1 |
| VPSRLW | Shifts words right logically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSUBB | Subtracts packed bytes, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPSUBD | Subtracts packed doublewords, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPSUBQ | Subtracts packed quadwords, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPSUBSB | Subtracts packed signed bytes with signed saturation. | AVX, AVX2, AVX10.1 |
| VPSUBSW | Subtracts packed signed words with signed saturation. | AVX, AVX2, AVX10.1 |
| VPSUBUSB | Subtracts packed unsigned bytes with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPSUBUSW | Subtracts packed unsigned words with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPSUBW | Subtracts packed words, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPTERNLOGD | Computes any bitwise function of three inputs, given as an 8-bit truth table in an immediate, masked at doubleword granularity. | AVX10.1 |
| VPTERNLOGQ | Computes any bitwise function of three inputs, given as an 8-bit truth table in an immediate, masked at quadword granularity. | AVX10.1 |
| VPTEST | Sets ZF if the AND of two XMM or YMM operands is all zeros and CF if the AND of the inverted first with the second is. | AVX |
| VPTESTMB | Sets a mask bit for each pair of bytes whose AND is not zero. | AVX10.1 |
| VPTESTMD | Sets a mask bit for each pair of doublewords whose AND is not zero. | AVX10.1 |
| VPTESTMQ | Sets a mask bit for each pair of quadwords whose AND is not zero. | AVX10.1 |
| VPTESTMW | Sets a mask bit for each pair of words whose AND is not zero. | AVX10.1 |
| VPTESTNMB | Sets a mask bit for each pair of bytes whose AND is zero. | AVX10.1 |
| VPTESTNMD | Sets a mask bit for each pair of doublewords whose AND is zero. | AVX10.1 |
| VPTESTNMQ | Sets a mask bit for each pair of quadwords whose AND is zero. | AVX10.1 |
| VPTESTNMW | Sets a mask bit for each pair of words whose AND is zero. | AVX10.1 |
| VPUNPCKHBW | Interleaves the high bytes of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKHDQ | Interleaves the high doublewords of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKHQDQ | Interleaves the high quadwords of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKHWD | Interleaves the high words of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKLBW | Interleaves the low bytes of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKLDQ | Interleaves the low doublewords of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKLQDQ | Interleaves the low quadwords of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKLWD | Interleaves the low words of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPXOR | Computes the bitwise XOR of two XMM or YMM sources into a separate destination (YMM with AVX2). | AVX, AVX2 |
| VPXORD | Computes the bitwise XOR of two vectors, masked at doubleword granularity. | AVX10.1 |
| VPXORQ | Computes the bitwise XOR of two vectors, masked at quadword granularity. | AVX10.1 |
| VRANGEPD | Computes the minimum, maximum, or value of smaller or larger magnitude of packed doubles, as an immediate selects along with the sign of the result. | AVX10.1 |
| VRANGEPS | Computes the minimum, maximum, or value of smaller or larger magnitude of packed singles, as an immediate selects along with the sign of the result. | AVX10.1 |
| VRANGESD | Computes the minimum, maximum, or smaller or larger magnitude of the low doubles, as an immediate selects; the rest come from the first source. | AVX10.1 |
| VRANGESS | Computes the minimum, maximum, or smaller or larger magnitude of the low singles, as an immediate selects; the rest come from the first source. | AVX10.1 |
| VRCP14PD | Approximates the reciprocal of packed doubles with a relative error below 2^-14. | AVX10.1 |
| VRCP14PS | Approximates the reciprocal of packed singles with a relative error below 2^-14. | AVX10.1 |
| VRCP14SD | Approximates the reciprocal of the low double of the second source with a relative error below 2^-14; the other elements come from the first source. | AVX10.1 |
| VRCP14SS | Approximates the reciprocal of the low single of the second source with a relative error below 2^-14; the other elements come from the first source. | AVX10.1 |
| VRCP28PD | Approximates the reciprocals of the packed doubles of a ZMM register, with a relative error below 2^-28. | AVX512ER |
| VRCP28PS | Approximates the reciprocals of the packed singles of a ZMM register to within 2^-28, then rounds them to single precision. | AVX512ER |
| VRCP28SD | Approximates the reciprocal of the low double to within 2^-28; the upper half comes from the first source. | AVX512ER |
| VRCP28SS | Approximates the reciprocal of the low single to within 2^-28 before rounding; the rest comes from the first source. | AVX512ER |
| VRCPBF16 | Approximates the reciprocal of each packed bfloat16 value with a relative error below 2^-8 + 2^-14. | AVX10.2 |
| VRCPPH | Approximates the reciprocal of packed half-precision values with a relative error below 2^-11 + 2^-14. | AVX10.1 |
| VRCPPS | Approximates the reciprocals of packed singles in an XMM or YMM register, with a relative error of at most 1.5 times 2^-12. | AVX |
| VRCPSH | Approximates the reciprocal of the second source's low half-precision value, relative error below 2^-11 + 2^-14; the rest come from the first source. | AVX10.1 |
| VRCPSS | Approximates the reciprocal of the low single to within 1.5 times 2^-12; the other elements come from the first source. | AVX |
| VREDUCEBF16 | Subtracts from each packed bfloat16 value its value rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.2 |
| VREDUCEPD | Subtracts from packed doubles their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.1 |
| VREDUCEPH | Subtracts from packed half-precision values their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.1 |
| VREDUCEPS | Subtracts from packed singles their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.1 |
| VREDUCESD | Subtracts from the low double of the second source its value rounded to the fraction bits an immediate gives; the rest come from the first source. | AVX10.1 |
| VREDUCESH | Subtracts from the second source's low half-precision value that value rounded to an immediate's precision; the rest come from the first source. | AVX10.1 |
| VREDUCESS | Subtracts from the low single of the second source its value rounded to the fraction bits an immediate gives; the rest come from the first source. | AVX10.1 |
| VRNDSCALEBF16 | Rounds each packed bfloat16 value to the number of fraction bits an immediate gives. | AVX10.2 |
| VRNDSCALEPD | Rounds packed doubles to the number of fraction bits and with the rounding mode that an immediate gives. | AVX10.1 |
| VRNDSCALEPH | Rounds packed half-precision values to the number of fraction bits and with the rounding mode that an immediate gives. | AVX10.1 |
| VRNDSCALEPS | Rounds packed singles to the number of fraction bits and with the rounding mode that an immediate gives. | AVX10.1 |
| VRNDSCALESD | Rounds the low double of the second source to the fraction bits and rounding mode an immediate gives; the rest come from the first source. | AVX10.1 |
| VRNDSCALESH | Rounds the second source's low half-precision value to the fraction bits and rounding mode an immediate gives; the rest come from the first source. | AVX10.1 |
| VRNDSCALESS | Rounds the low single of the second source to the fraction bits and rounding mode an immediate gives; the rest come from the first source. | AVX10.1 |
| VROUNDPD | Rounds packed doubles in an XMM or YMM register to integral values, with the rounding mode of an immediate or MXCSR. | AVX |
| VROUNDPS | Rounds packed singles in an XMM or YMM register to integral values, with the rounding mode of an immediate or MXCSR. | AVX |
| VROUNDSD | Rounds the low double of the second source to an integral value, by an immediate or MXCSR; the upper half comes from the first. | AVX |
| VROUNDSS | Rounds the low single of the second source to an integral value, by an immediate or MXCSR; the rest comes from the first. | AVX |
| VRSQRT14PD | Approximates the reciprocal square root of packed doubles with a relative error below 2^-14. | AVX10.1 |
| VRSQRT14PS | Approximates the reciprocal square root of packed singles with a relative error below 2^-14. | AVX10.1 |
| VRSQRT14SD | Approximates the reciprocal square root of the second source's low double, relative error below 2^-14; the rest come from the first source. | AVX10.1 |
| VRSQRT14SS | Approximates the reciprocal square root of the second source's low single, relative error below 2^-14; the rest come from the first source. | AVX10.1 |
| VRSQRT28PD | Approximates the reciprocal square roots of the packed doubles of a ZMM register, with a relative error below 2^-28. | AVX512ER |
| VRSQRT28PS | Approximates the reciprocal square roots of packed singles to within 2^-28, then rounds them to single precision. | AVX512ER |
| VRSQRT28SD | Approximates the reciprocal square root of the low double to within 2^-28; the upper half comes from the first source. | AVX512ER |
| VRSQRT28SS | Approximates the reciprocal square root of the low single to within 2^-28 before rounding; the rest comes from the first source. | AVX512ER |
| VRSQRTBF16 | Approximates the reciprocal square root of each packed bfloat16 value with a relative error below 2^-8 + 2^-14. | AVX10.2 |
| VRSQRTPH | Approximates the reciprocal square root of packed half-precision values with a relative error below 2^-11 + 2^-14. | AVX10.1 |
| VRSQRTPS | Approximates the reciprocal square roots of packed singles in an XMM or YMM register, to within 1.5 times 2^-12. | AVX |
| VRSQRTSH | Approximates 1/sqrt(x) for the second source's low half-precision value, relative error below 2^-11 + 2^-14; the rest come from the first source. | AVX10.1 |
| VRSQRTSS | Approximates the reciprocal square root of the low single to within 1.5 times 2^-12; the other elements come from the first source. | AVX |
| VSCALEFBF16 | Multiplies each packed bfloat16 value by 2 raised to the floor of the corresponding value of the second source. | AVX10.2 |
| VSCALEFPD | Multiplies packed doubles by 2 raised to the floor of the matching values of the second source. | AVX10.1 |
| VSCALEFPH | Multiplies packed half-precision values by 2 raised to the floor of the matching values of the second source. | AVX10.1 |
| VSCALEFPS | Multiplies packed singles by 2 raised to the floor of the matching values of the second source. | AVX10.1 |
| VSCALEFSD | Multiplies the low double by 2 raised to the floor of the low value of the second source; the other elements come from the first source. | AVX10.1 |
| VSCALEFSH | Multiplies the low half-precision value by 2 to the floor of the second source's low value; the other elements come from the first source. | AVX10.1 |
| VSCALEFSS | Multiplies the low single by 2 raised to the floor of the low value of the second source; the other elements come from the first source. | AVX10.1 |
| VSCATTERDPD | Stores doubles to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VSCATTERDPS | Stores singles to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VSCATTERPF0DPD | Prefetches, with intent to write, the doubles that a vector of doubleword indices addresses into the first-level cache. | AVX512PF |
| VSCATTERPF0DPS | Prefetches, with intent to write, the singles that a vector of doubleword indices addresses into the first-level cache. | AVX512PF |
| VSCATTERPF0QPD | Prefetches, with intent to write, the doubles that a vector of quadword indices addresses into the first-level cache. | AVX512PF |
| VSCATTERPF0QPS | Prefetches, with intent to write, the singles that a vector of quadword indices addresses into the first-level cache. | AVX512PF |
| VSCATTERPF1DPD | Prefetches, with intent to write, the doubles that a vector of doubleword indices addresses into the second-level cache. | AVX512PF |
| VSCATTERPF1DPS | Prefetches, with intent to write, the singles that a vector of doubleword indices addresses into the second-level cache. | AVX512PF |
| VSCATTERPF1QPD | Prefetches, with intent to write, the doubles that a vector of quadword indices addresses into the second-level cache. | AVX512PF |
| VSCATTERPF1QPS | Prefetches, with intent to write, the singles that a vector of quadword indices addresses into the second-level cache. | AVX512PF |
| VSCATTERQPD | Stores doubles to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VSCATTERQPS | Stores singles to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VSHA512MSG1 | Performs the first half of the SHA-512 message schedule computation for the next four message quadwords. | SHA512 |
| VSHA512MSG2 | Completes the SHA-512 message schedule computation for the next four message quadwords. | SHA512 |
| VSHA512RNDS2 | Performs two rounds of SHA-512 (and SHA-384) on the working state, using precomputed message and round-constant sums. | SHA512 |
| VSHUFF32X4 | Picks 128-bit blocks of singles from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFF64X2 | Picks 128-bit blocks of doubles from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFI32X4 | Picks 128-bit blocks of doublewords from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFI64X2 | Picks 128-bit blocks of quadwords from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFPD | Picks doubles from the two sources for each position within each 128-bit lane, as an immediate selects. | AVX, AVX10.1 |
| VSHUFPS | Picks singles from the two sources for each position within each 128-bit lane, as an immediate selects. | AVX, AVX10.1 |
| VSM3MSG1 | Performs the first part of the SM3 message expansion for the next four message words. | SM3 |
| VSM3MSG2 | Completes the SM3 message expansion for the next four message words. | SM3 |
| VSM3RNDS2 | Performs two rounds of the SM3 hash function, starting at the round number in an immediate. | SM3 |
| VSM4KEY4 | Performs four rounds of SM4 key expansion in each 128-bit lane. | SM4 |
| VSM4RNDS4 | Performs four rounds of SM4 encryption in each 128-bit lane. | SM4 |
| VSQRTBF16 | Computes the square root of each packed bfloat16 value, rounding to nearest, with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VSQRTPD | Computes the square root of packed doubles. | AVX, AVX10.1 |
| VSQRTPH | Computes the square root of packed half-precision values. | AVX10.1 |
| VSQRTPS | Computes the square root of packed singles. | AVX, AVX10.1 |
| VSQRTSD | Computes the square root of the low double of the second source; the other elements come from the first source. | AVX, AVX10.1 |
| VSQRTSH | Computes the square root of the low half-precision value of the second source; the other elements come from the first source. | AVX10.1 |
| VSQRTSS | Computes the square root of the low single of the second source; the other elements come from the first source. | AVX, AVX10.1 |
| VSTMXCSR | Stores the MXCSR register, the SSE control and status bits, to memory; the VEX form of STMXCSR. | AVX |
| VSUBBF16 | Subtracts packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VSUBPD | Subtracts packed doubles. | AVX, AVX10.1 |
| VSUBPH | Subtracts packed half-precision values. | AVX10.1 |
| VSUBPS | Subtracts packed singles. | AVX, AVX10.1 |
| VSUBSD | Subtracts the low doubles; the other elements come from the first source. | AVX, AVX10.1 |
| VSUBSH | Subtracts the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VSUBSS | Subtracts the low singles; the other elements come from the first source. | AVX, AVX10.1 |
| VTESTPD | Sets ZF and CF like VPTEST, but from the sign bits of the packed doubles alone. | AVX |
| VTESTPS | Sets ZF and CF like VPTEST, but from the sign bits of the packed singles alone. | AVX |
| VUCOMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | AVX, AVX10.1 |
| VUCOMISH | Compares the low half-precision values and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | AVX10.1 |
| VUCOMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | AVX, AVX10.1 |
| VUCOMXSD | Compares the low double-precision values of two operands like VCOMXSD but signals an invalid exception only for signaling NaNs. | AVX10.2 |
| VUCOMXSH | Compares the low half-precision values of two operands like VCOMXSH but signals an invalid exception only for signaling NaNs. | AVX10.2 |
| VUCOMXSS | Compares the low single-precision values of two operands like VCOMXSS but signals an invalid exception only for signaling NaNs. | AVX10.2 |
| VUNPACKB | Unpacks tightly packed 2- to 7-bit fields into bytes, zero- or sign-extended, with the field size and start given by an immediate. | AVX10_V2_AUX |
| VUNPCKHPD | Interleaves the high doubles of each 128-bit lane of two sources. | AVX, AVX10.1 |
| VUNPCKHPS | Interleaves the high singles of each 128-bit lane of two sources. | AVX, AVX10.1 |
| VUNPCKLPD | Interleaves the low doubles of each 128-bit lane of two sources. | AVX, AVX10.1 |
| VUNPCKLPS | Interleaves the low singles of each 128-bit lane of two sources. | AVX, AVX10.1 |
| VXORPD | Computes the bitwise XOR of packed doubles. | AVX, AVX10.1 |
| VXORPS | Computes the bitwise XOR of packed singles. | AVX, AVX10.1 |
| VZEROALL | Zeroes vector registers 0 to 15 (0 to 7 outside 64-bit mode) in full. | AVX |
| VZEROUPPER | Zeroes the bits above 127 of vector registers 0 to 15, which compilers do before running or calling code that may use legacy SSE. | AVX |
| WBINVD | Writes every modified line of the caches back to memory and invalidates the caches; ring 0 only. | System |
| WBNOINVD | Writes every modified line of the caches back to memory but keeps the lines cached; ring 0 only. | WBNOINVD |
| WRFSBASE | Writes the FS base from a register, so a thread can change its TLS pointer without a system call; 64-bit mode, with CR4.FSGSBASE. | FSGSBASE |
| WRGSBASE | Writes the GS base from a register; 64-bit mode, when the kernel set CR4.FSGSBASE. | FSGSBASE |
| WRMSR | Writes EDX:EAX to the model-specific register that ECX selects; ring 0 only and, unlike WRMSRNS, serializing. | System |
| WRMSRLIST | Writes up to 64 model-specific registers from a table in memory to the addresses listed in a second table, selected by a bit mask in RCX. | MSRLIST |
| WRMSRNS | Writes a model-specific register like WRMSR but without serializing the processor; the MSR_IMM form takes the MSR number as an immediate. | WRMSRNS, MSR_IMM, APX |
| WRPKRU | Writes PKRU from EAX, changing which of the 16 protection keys allow access and writes, without a system call; ECX and EDX must be zero. | PKU |
| WRSSD | Writes a 32-bit value to the current privilege level's shadow stack, where the operating system allows such writes. | CET, APX |
| WRSSQ | Writes a 64-bit value to the current privilege level's shadow stack, where the operating system allows such writes. | CET, APX |
| WRUSSD | Lets ring-0 code write a 32-bit value to a user-mode shadow stack. | CET, APX |
| WRUSSQ | Lets ring-0 code write a 64-bit value to a user-mode shadow stack. | CET, APX |
| XABORT | Aborts an RTM transaction, discarding its effects and resuming at the XBEGIN fallback with an 8-bit reason code in EAX. | RTM |
| XADD | Exchanges a register with the destination and stores their sum in the destination; with LOCK it is the atomic fetch-and-add. | General-purpose |
| XBEGIN | Starts an RTM transaction; if it aborts, its effects are rolled back and execution goes to the fallback address, with the reason in EAX. | RTM |
| XCHG | Swaps two operands; with a memory operand it is atomic even without a LOCK prefix. | General-purpose |
| XCRYPTCBC | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in CBC mode; rAX, rBX and rDX point to IV, key and control word; VIA PadLock. | VIA PadLock |
| XCRYPTCFB | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in CFB mode; rAX, rBX and rDX point to IV, key and control word; VIA PadLock. | VIA PadLock |
| XCRYPTCTR | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in counter mode; rAX, rBX and rDX point to counter, key and control word. | VIA PadLock |
| XCRYPTECB | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in ECB mode, the key at [rBX] and a control word at [rDX]; VIA PadLock. | VIA PadLock |
| XCRYPTOFB | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in OFB mode; rAX, rBX and rDX point to IV, key and control word; VIA PadLock. | VIA PadLock |
| XEND | Commits an RTM transaction, making all of its memory updates visible at once. | RTM |
| XGETBV | Reads the extended control register that ECX selects into EDX:EAX; XCR0 says which state components the OS lets XSAVE manage. | XSAVE |
| XLAT | Replaces AL with the byte at RBX plus AL, a table lookup; XLATB is the spelling without operands. | General-purpose |
| XOR | Computes the bitwise exclusive OR of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| XORPD | Computes the bitwise XOR of two XMM operands, as packed doubles; with the same register twice it zeroes it. | SSE2 |
| XORPS | Computes the bitwise XOR of two XMM operands, as packed singles; with the same register twice it zeroes it. | SSE |
| XRESLDTRK | Ends a TSXLDTRK region of an RTM transaction, so that later loads join the transaction's read set again. | TSXLDTRK |
| XRSTOR | Restores the state components that XCR0 and EDX:EAX select from an XSAVE area, setting those the area marks unused to their initial state. | XSAVE |
| XRSTORS | Restores user and supervisor state components from a compacted XSAVE area written by XSAVES; ring 0 only. | XSAVES |
| XSAVE | Saves the state components that XCR0 and EDX:EAX select, such as the x87, SSE and AVX registers, to a 64-byte aligned XSAVE area. | XSAVE |
| XSAVEC | Saves selected state components in the compacted format of the XSAVE area, leaving out those in their initial state. | XSAVEC |
| XSAVEOPT | Saves selected state components like XSAVE but may skip those unchanged since the last XRSTOR or in their initial state. | XSAVEOPT |
| XSAVES | Saves selected user and supervisor state components in the compacted format, skipping unchanged and initial ones; ring 0 only. | XSAVES |
| XSETBV | Writes EDX:EAX to the extended control register that ECX selects, such as XCR0, which enables AVX and other XSAVE state; ring 0 only. | XSAVE |
| XSHA1 | Hashes the data at [rSI] with SHA-1 into the state at [rDI]; rCX gives the total length and rAX the bytes already hashed; VIA PadLock. | VIA PadLock |
| XSHA256 | Hashes the data at [rSI] with SHA-256 into the state at [rDI]; rCX gives the total length and rAX the bytes already hashed; VIA PadLock. | VIA PadLock |
| XSTORE | Stores random bytes from the processor's random number generator at [rDI], at the rate EDX selects, and returns their count in EAX; VIA PadLock. | VIA PadLock |
| XSUSLDTRK | Starts a region of an RTM transaction whose loads stay out of its read set, so they cannot cause conflicts. | TSXLDTRK |
| XTEST | Clears ZF inside an RTM or HLE transaction and sets it outside one. | RTM |
表の読み方
表は Intel のマニュアルの表記に従い、XED が記録している情報のためにいくつかの表記を加えています。
命令
オペランドは Intel の順序で、デスティネーションが先です。
r8,r16,r32,r64- その幅の汎用レジスター。
r16/32/64は、オペランドサイズがプレフィックスで選ばれることを意味します。66 なら 16 ビット、REX.W (または EVEX.W) なら 64 ビット、それ以外は 32 ビットです。 m8からm512,m16/32/64- そのビット数のメモリオペランド。
imm8,imm16/32,imm64- 命令の中にエンコードされた即値。
rel8,rel32,rel16/32- 次の命令からの符号付きオフセットで表した分岐先。
m16:16/32/64,ptr16:16/32- ファーポインター (far pointer)。16 ビットのセグメントセレクターと 16、32、または 64 ビットのオフセットで、メモリ上にあるか即値です。
AL,eAX,rAX,DX- 固定のレジスター。オペランドサイズによって、
eAXは AX または EAX、rAXは AX、EAX、または RAX です。 sreg,cr,dr- セグメントレジスター、制御レジスター、またはデバッグレジスター。
m- LEA のように、アドレスだけが意味を持つメモリオペランド。
mem,m512byte- 保持する内容で名付けたメモリ領域。保存する状態によってサイズが変わる XSAVE 領域、または FXSAVE の 512 バイトです。
m16&32,m16&64,m16&16,m32&32- メモリ上の 2 つの値。LGDT が読み込むような 16 ビットのリミットとベース、または BOUND の 2 つの境界です。
bnd,mib- MPX のバウンドレジスターと、MPX がベースレジスターとインデックスレジスターを別々に使うメモリオペランド。
st(i),ST(0),mm- レジスタースタックの先頭から数えた x87 レジスター、先頭そのもの、および 64 ビットの MMX レジスター。
m32fp,m16int,m80bcd,m28byte- サイズと型で区別した x87 のメモリオペランド。浮動小数点値、符号付き整数、18 桁のパック BCD 整数、または x87 の環境や状態で、最後のものはオペランドサイズによってサイズが変わります。
xmm,ymm,zmm,k,tmm- 128、256、または 512 ビットのベクトルレジスター、AVX-512 のマスクレジスター、または AMX のタイルレジスター。
{k},{k}{z}- デスティネーションはマスクレジスターに従って書き込まれます。
{z}があると、マスクされた要素は保持される代わりにゼロにできます。 m512/m32bcst- メモリ上の完全なベクトル、またはすべての位置にブロードキャストされる 1 つの要素 (EVEX.b がセット)。
{er},{sae}- レジスター形式が命令の中で丸めモードを受け付ける (埋め込み丸め) か、浮動小数点例外を抑制します。
vm32x,vm64z- ギャザーとスキャッターのためのアドレスのベクトル。xmm、ymm、または zmm レジスターの中の 32 または 64 ビットのインデックスです (VSIB アドレス指定)。
sibmem- SIB バイトでエンコードしなければならないメモリオペランド。AMX のタイルのロードとストアは、そのインデックスレジスターを行のストライドとして使います。
{dfv}- APX の CCMP と CTEST が条件が偽のときにセットするフラグで、命令の中にエンコードされます。
cc,scc- 条件コード。CMOVZ と CMOVNZ のように条件だけが異なるニーモニックは 1 つのページを共有します。条件はオペコードの一部 (
40+cc) か、EVEX プレフィックスの一部 (SC=scc) です。 LOCK,REP- その命令形式はプレフィックスを伴います。XED はこれらを別々の命令として挙げていますが、ここでは基本のニーモニックのページに載せています。MOVS のページにある MOVSB から MOVSQ のように、1 つの命令のオペランドサイズごとの綴りも同様です。
エンコーディング
66,F2,F3,NP- オペコードの一部であるプレフィックス。NP はそのどれも許されないことを意味します。
67- アドレスサイズプレフィックス。64 ビットモードで ECX をテストする JECXZ のように、モードのデフォルトより小さいアドレスサイズを使う命令形式のためのものです。
REX.W,REX2- W がセットされた REX プレフィックス、または APX の 2 バイトの REX2 プレフィックス (D5)。
0F,0F 38,0F 3A- レガシのオペコードマップのエスケープバイト。
VEX.256.66.0F38.W0- フィールドを伴う VEX または EVEX プレフィックス。ベクトル長 (128、256、512。ベクトルオペランドのない命令では
LZまたはLLZはゼロ、L1は 1 でなければならず、LIGは無視されることを示します)、暗黙のプレフィックス、オペコードマップ (0F、0F38、0F3A、または MAP4 から MAP7)、および W ビット (W0、W1、無視される場合はWIG) です。 SCALABLE- レガシ命令の APX 形式では、REX.W と 66 と同じように、EVEX.W が 64 ビットのオペランドを、暗黙の 66 プレフィックスが 16 ビットのオペランドを選びます。
/r,/0から/7,C0- reg フィールドにレジスターオペランドを持つ ModR/M バイト、オペコードを拡張する固定値を reg フィールドに持つ ModR/M バイト、または固定の ModR/M バイト。
+r,+cc- オペコードバイトに加えるレジスター番号または条件コード。
C0+i- x87 レジスター。ST(i) の番号 i を 2 バイト目に加えます (
D8 C0+iは FADD ST(0), ST(i) です)。 ib,iw,id,io,/is4- 1、2、4、または 8 バイトの即値。
iw/idはオペランドサイズによって決まります。/is4は上位 4 ビットでレジスターを指定する即値バイトです。 ND=1,NF=1,NF=0/1- EVEX プレフィックスの APX のビット。ND は新しいデータデスティネーションを選び、NF はフラグの更新を抑制します。
NF=0/1は、その命令形式が両方の形で存在することを意味します。 (without BMI1)- そのバイト列がこの命令を意味するのは、指定された機能を持たないプロセッサーでだけです。その機能を持つプロセッサーでは別の命令になります。F3 0F BC は、BMI1 がなければ BSF、あれば TZCNT です。
タグ
- NDD
- APX の新しいデータデスティネーション (new data destination)。結果は別のレジスターに入り、ほかのオペランドは読み取られるだけです。
- NF
- APX の「no flags」。命令は算術フラグを変更しません。
- ZU
- APX の「zero upper」。デスティネーションレジスターは全体が書き込まれ、結果より上はゼロになります。
- 64-bit mode only, not in 64-bit mode
- その命令形式を使える場所 (64 ビットモードのみ、64 ビットモード以外)。APX 形式は常に 64 ビットモード専用です。
- undocumented
- Intel のマニュアルには載っていないが、XED がこの命令としてデコードするエンコーディング (文書化されていないエンコーディング)。たとえば FSTP ST(i) の x87 の別名である DF D0+i です。
要件
各命令形式は XED の ISA セットの 1 つに属します。この列は、それを有効にする CPUID の機能を示します。選択肢がある場合は、そのどれか 1 つで十分です。たとえば AVX-512 の形式には、その AVX-512 の機能ビットか AVX10.1 のどちらかが必要です。各ページは、正確な CPUID ビットと、XED のチップモデルが各 ISA セットに割り当てるプロセッサーを挙げ、その後にこのサイトの CPU データから Zen 2 より後の AMD のプロセッサーを挙げています。
レイテンシとスループット
命令形式の後の表は、LLVM 23.1.2 (コミット 85ac56026243)
のスケジューリングモデルが各命令形式について示す値を、llvm-mca が報告するとおりに示します。レイテンシは入力から結果までのサイクル数、逆数スループットは多数の独立した命令が続くときの 1 命令あたりのサイクル数です。その下には、モデルがその命令形式を割り当てるポートまたはユニットを示します。たとえば p01 は Intel のコアのポート 0 と 1、FP2 FP3 は AMD のコアの浮動小数点パイプのうち 2 つです。これらは LLVM のコンパイラーがコードのスケジューリングに使うモデルであって測定値ではなく、誤っていることもあります。メモリ形式のレイテンシはアドレスから数えるのでロードを含み、そのポートにはロードやストア自体のユニットは含まれません。モデルがポートを示していないセルにはポートが表示されず、レジスター間の移動にレイテンシまたは逆数スループット 0 を与えるモデルもあります。
列は 1 つのオペランドサイズでの命令形式です。すべてのモデルで同じ数値になる命令形式は列を共有し、EVEX 形式のマスク付き、ゼロ化、ブロードキャスト、丸めの各バリアントも同様に列を共有します。ただしタイミングが異なるものは別の列になり、「with a mask」などのラベルが付きます。行はモデル、またはすべての列で同じ数値になるモデルの集まりで、それぞれのモデルが対象としたプロセッサーの名前が付いています。llvm-mca はどの命令もどのモデルでもタイミングを計算するため、モデルにセルがあるのは、ページのプロセッサー一覧が示すとおり、そのモデル自身のプロセッサーのどれかが持つ命令形式だけです。それ以外はダッシュで示します。ページがサイズの予算を超えそうな場合、表はロードまたはストアだけを行う命令形式のポート、またはすべてのポートを省き、キャプションでそのことを示します。
LLVM には Zen 5 や Zen 6 専用のモデルがなく、これらを Zen 4 のモデルでスケジュールするため、Zen 4 の行がこれらも表します。AMD の最適化ガイド 58455 に含まれる Zen 5 のレイテンシのスプレッドシートは、新しいコアの幅が広い点でその行と異なります。ADD のような単純な整数命令は 6 つの ALU で 1 サイクルに 6 個実行されますが、モデルは 4 個としています (行 1970)。2 オペランドの IMUL は 3 つの乗算器で 1 サイクルに 3 個ですが、モデルは 1 個です (行 2021)。VADDPS のような ZMM 形式は 512 ビットのデータパスで 1 サイクルに 2 個ですが、Zen 4 と同じようにそれらを半分に分割するモデルは 1 個です (行 3)。ADDPS のような浮動小数点加算は 2 サイクルですが、モデルは 3 サイクルとしています (行 1450)。PSHUFD のような単純なシャッフルは 4 つのパイプで実行されますが、モデルでは 2 つです (行 1581)。セルがそのスプレッドシートとも AMD の Zen 4 のもの (57647) とも食い違う場合、モデルは Zen 4 についても誤っている可能性が高いです。その場合セルには番号付きの印があり、表の下の注で両方のスプレッドシートの行を示します。モデルが自身の出典と矛盾するセルも同様です。まだすべてのページを確認したわけではありません。
モデルの 2 つの選択はページ上で印を付けていません。Alder Lake、Sapphire Rapids、Lunar Lake のモデルはすべてのストアに 12 サイクルのレイテンシを与えています (X86SchedAlderlakeP.td, line 420)。ほかのモデルは 1 です。Piledriver のモデルはアラインされた 256 ビットのストアに逆数スループット 18 を与えており、これは Agner Fog が測定した 17 サイクルに 1 回というそのようなストアの値 (彼のマイクロアーキテクチャーのガイド、21.9 節) に近い値ですが、アラインされていない 256 ビットのストアには 1 を与えています。
| 行 | LLVM のモデル | 対象 | 流用先 |
|---|---|---|---|
| Sandy Bridge | SandyBridgeModel | Sandy Bridge, Ivy Bridge | Core (Merom, Conroe), Penryn, Nehalem, Westmere |
| Haswell | HaswellModel | Haswell | Knights Landing, Knights Mill |
| Broadwell | BroadwellModel | Broadwell | |
| Skylake | SkylakeClientModel | Skylake, Kaby Lake, Coffee Lake, Comet Lake | |
| Skylake-SP | SkylakeServerModel | Skylake-SP, Cascade Lake, Cooper Lake | Cannon Lake |
| Ice Lake | IceLakeModel | Ice Lake (client), Ice Lake (server) | Tiger Lake, Rocket Lake |
| Alder Lake | AlderlakePModel | Alder Lake, Raptor Lake | Meteor Lake, Arrow Lake, Panther Lake, Nova Lake, Gracemont, Sierra Forest, Clearwater Forest |
| Sapphire Rapids | SapphireRapidsModel | Sapphire Rapids, Emerald Rapids | Granite Rapids, Diamond Rapids |
| Lunar Lake | LunarlakePModel | Lunar Lake | |
| Bonnell | AtomModel | Bonnell, Saltwell | |
| Silvermont | SLMModel | Silvermont, Airmont | Goldmont, Goldmont Plus, Tremont |
| Piledriver | BdVer2Model | Piledriver | Bulldozer, Steamroller |
| Zen | Znver1Model | Zen, Zen+, Dhyana | Excavator |
| Zen 2 | Znver2Model | Zen 2 | |
| Zen 3 | Znver3Model | Zen 3 | |
| Zen 4 | Znver4Model | Zen 4 | Zen 5, Zen 6 |
| Jaguar | BtVer2Model | Jaguar, Puma |
どの表の行にも使われていないモデル:
GenericPostRAModel(NetBurst (Prescott, Nocona)): it gives no latencies or units of its own.C864GM4Model、C864GM7ModelとC864GM8Model: Hygon's C86-4G processors have no page under /cpus/.- K8 (Hammer): X86.td defines k8 with a Proc line, which has no scheduling model.
- K10 (Family 10h): X86.td defines amdfam10 with a Proc line, which has no scheduling model.
- Bobcat: X86.td defines btver1 with a Proc line, which has no scheduling model.
- LuJiaZui, Century Avenue (Shijidadao): X86.td has no -mcpu for Zhaoxin's processors.
データフロー
ベクトル命令のページには、ソースの要素がどこへ行くかを図示しています。各行は 1 つのオペランドで、Intel のマニュアルが番号を付けるとおりに名付けています (xmm1 は 1 番目のオペランドで、通常はデスティネーションです)。要素 0 は右端にあります。結果の名前は青で、各ソースにはそれぞれの文字と色があります。要素を同じように移動する命令形式は 1 つの図を共有し、その図は 1 つのベクトル長で描いてほかの長さについては注記します。128 ビットの各レーンで繰り返されるパターンは 1 つのレーンについて描きます。即値、インデックスのベクトル、マスクなどの制御値によって結果が変わる場合、図は例を使って説明します。すべての例は AMD EPYC 9645 (Zen 5) プロセッサーで、その命令自体として、またはそのプロセッサーがその命令を持たない場合は要素を同じように移動する別の命令として実行し、図は出てきた結果を示しています。XOP の並べ替え命令の例は、手元のどのプロセッサーもそれを持たないため実行していません。ページの疑似コードがその結果を求めており、図にもそのことを記しています。各図の下の文章も同じことを述べ、最後に描いた結果を要素ごとに、上位から順に示します。
図は最大で 16 列、スマートフォンでは最大で 8 列です。スマートフォンでは、それより多くの要素を持つ行は 2 段になり、上位の要素が上に置かれ、下の段は半列分右にずらして、各ワイヤーがもう一方の段を 2 つのセルの間で通るようにします。16 列ではセルが狭すぎてラベルが収まらない画面でも、同じように 2 段で描きます。4 ビット要素への変換のように、2 段に収まらないレジスターの残りのゼロ化部分は、上の段の左端の 1 つのセルにまとめます。
a3,b0- ソース a の要素 3、またはソース b の要素 0。結果の要素がどこから来るかを示し、ワイヤーが両者を結びます。
r0,sum,+=- ワイヤーの来る要素から計算した要素。
sumはそれらのグループを加算し、+=はそれらをデスティネーションの元の値に加算します。 0、灰色- ゼロにされる要素。
- 斜線
- そのまま残される要素。マージによるマスク処理でマスクされた要素、または書き込まれないメモリです。
- 塗りつぶした点と白抜きの点
- マスクレジスター
k1のビット。1 が塗りつぶし、0 が白抜きです。各要素のワイヤーはそのビットを通ります。 …- 行は左に続きます。下位の要素だけを描いています。
- バー
- ウィンドウ。結果の 1 つの要素の計算に使うソースのバイトまたはビットで、たとえば絶対差の和の各ワードが取る 4 バイトです。各バーのワイヤーはバーの上の点から始まり、重なるバーは上下に並べます。
- 目盛り
- ダブルワード単位で描いたソースのバイト、またはバイト単位で描いたソースのビット。
- 灰色の上部
- 幅を広げた要素の拡張部分。ゼロ、または符号ビットのコピーです。
動作
これまでに対応した命令のページでは、各命令形式が何をするかを独自の疑似コードで示しています。これはテストが実行する Python の小さなサブセットです。各ブロックは上に名前を挙げた命令形式のグループを扱い、命令形式が 64 ビットモードの外にしか存在しない場合を除き、64 ビットモードでの動作を記述します。ブロックの下の行は、それを実行したプロセッサーを示します。エッジケースとランダムな入力に対するプロセッサーの結果を、たとえば AMD EPYC 9645 (Zen 5) 上でプローブで記録し、テストは同じ入力でブロックを実行して同じ結果になることを求めます。両者が食い違う場合はプロセッサーが正しいとします。制御レジスターへの移動のようにユーザーモードで実行できないブロックも同じように書き、実行していないことを記します。手元のどのプロセッサーも持たない APX 形式も同様です。プローブが実行される CPL 3 での特権命令や、ポートへのアクセス権のない IN のように、ブロックのすべてのケースが例外を発生させた場合は、その行にそう記します。それらのケースが確認したのは最初に来るチェックであり、それを通過した後に命令が何をするかではありません。CPUID がその拡張をサポートしていないと報告したプロセッサーで、そのバイト列をプロセッサーがどう扱うかを見るためにプローブが実行した命令の行も同様です。結果はほとんどが #UD で、ENDBR64 のようにバイト列がヒント命令である場合は何も起きません。それらのケースはその命令の機能チェックを確認したものです。プローブはハイパーバイザーの下で実行されるため、ハイパーバイザーがプロセッサーの持つ機能を CPUID から隠している場合があります。
dest,src,count- 構文のオペランドで、構文の順序どおりです。
dest.read()とdest.write(v)はオペランドを読み書きします。dest + srcのように値として使ったオペランドは読み取られます。.bitsはその幅、.is_memoryはメモリ上にあるかどうか、.numberは CR4 のようなレジスターの番号です。LEA のsrc.addressはそれが計算するアドレスで、ベースとインデックスかけるスケールとディスプレースメントの和をアドレスサイズで求めたものです。メモリは読み取りません。 rax,eax,ax,al,ah- 名前で指定したレジスター。32 ビットレジスターへの書き込みは、その 64 ビットレジスターのビット 63:32 をクリアします。8 ビットまたは 16 ビットのレジスターへの書き込みはほかのビットを保持します。APX の NDD 形式の新しいデスティネーション、および ZU 形式や CFCMOVcc のデスティネーションは、どのオペランドサイズでも全体が書き込まれ、ビット 63:OSIZE はクリアされます。
rAX- オペランドサイズのアキュムレーター。構文の表記に従い AL、AX、EAX、または RAX です。
aCX,aSI,aDI- アドレスサイズでの RCX、RSI、RDI。ストリング命令と LOOP のカウントとポインターで、67 プレフィックスがあると ECX、ESI、EDI になります。
rip- 次の命令のアドレス。命令自身のアドレスに命令の長さを足したもので、CALL がプッシュする値です。
ripに代入するとそこへジャンプします。 cf,pf,af,zf,sf,of- ステータスフラグで、0 または 1。
flags = add_flags(a, b)は 6 つすべてを加算と同じようにセットし、sub_flagsは減算と同じようにセットします。 df,tf,if_,iopl,ac,id,rflags- RFLAGS のその他のフラグを名前で指定したもの。IF は
if_で (ifは Python の予約語です)、IOPL は 0 から 3 の数値です。rflagsはレジスター全体を、PUSHF がプッシュするとおりの数値として表します。 UNDEFINED- 命令がフラグ、レジスター、またはメモリを未定義のままにする場合に、それらが保持する値。プロセッサーは何らかの値を残しますが、それに依存してはならず、テストもそれを比較しません。
OSIZE,nf,CPL,dfv- ビット単位のオペランドサイズ (8、16、32、または 64)、APX 形式の NF ビット、現在の特権レベル、および CCMPscc と CTESTscc の
{dfv}。最後のものは条件が偽のときにセットするフラグで、OF、SF、ZF、CF をビット 3 から 0 に置いたものです。 cond(CC)- フラグが条件付き命令の条件を満たすとき 1。CMOVcc、SETcc、Jcc とその仲間のページはすべての条件に対して 1 つのブロックを持ち、
CCはニーモニックの中の条件を小文字で表したものです。たとえば CMOVNBE (CMOVA とも綴ります) ではnbeです。o、b、z、s、pは OF、CF、ZF、SF、PF が 1 のときに成り立ち、beは CF または ZF が 1 のとき、lは SF と OF が異なるとき、leは ZF が 1 であるか SF と OF が異なるときに成り立ちます。前にnが付く条件 (nbe) は、付かない条件が成り立たないときに成り立ちます。CCMPscc と CTESTscc のtとfは、常に成り立つ条件と決して成り立たない条件です。cond(CC, f)は、命令の前のフラグではなく、f = sub_flags(a, b)のようにブロックが計算したフラグをテストします。 sext(x),signed(x),low(x),msb(x),parity(x)- その幅からオペランドサイズに符号拡張した
x(即値は imm8 のようにエンコードされた幅から)、その幅の符号付き数としてのx(0xFF の imm8 は -1 になります)、その下位 OSIZE ビット、その最上位ビット、および PF と同じく、下位バイトの 1 のビットの数が偶数のとき 1 になる値。 fault(GP, 0)- 命令が例外 (ここでは #GP(0)) を発生させ、レジスターを 1 つも書き込みません。例外は # を付けない名前で表します。DE、DB、BP、OF、BR、UD、NM、TS、NP、SS、GP、PF、MF、AC、XM、CP です。
load_segment(dest, sel),load_segment(fs, sel)- セグメントレジスターに、セレクターと、それが GDT または LDT の中で指すディスクリプターを読み込みます。ディスクリプターがテーブルの範囲内にあり、その型、特権レベル (RPL、DPL、CPL)、プレゼントビットが読み込みを許すことを確認し、そうでなければ #GP、#SS、または #NP を発生させます。ヌルセレクターは DS、ES、FS、GS を使用不能な状態で読み込みますが、CPL 3 の SS には使えません。詳細な規則は Intel SDM の Volume 3 にあります。レジスターはオペランドであるか、構文がそれを省いている LFS の
fsのように名前で指定します。 gate(n),descriptor(sel)- 割り込みディスクリプターテーブル (IDT) のエントリ n (16 バイト) と、セレクターが GDT (TI ビットがセットされていれば LDT) の中で指す 8 バイトのセグメントディスクリプター。ブロックがフィールドを取り出す数値として表します。ゲートでは型がビット 43:40 (1110b は割り込みゲート、1111b はトラップゲート)、DPL が 46:45、P (プレゼント) が 47 にあります。セグメントでは型が 43:40 (コードならビット 43 がセットされ、ビット 42 がコンフォーミング (conforming)、41 が読み取り可能を表します。データならエクスパンドダウン (expand-down) と書き込み可能を表します)、S が 44、DPL が 46:45、P が 47、L (64 ビットコード) が 53 にあります。テーブルのリミットを超えるエントリは #GP を発生させ、エラーコードはゲートなら 8n + 2、ディスクリプターならセレクターです。
in_table(sel),gdtr,idtr,ldtr,trin_table(sel)は、セレクターが指すディスクリプターがテーブルの範囲内にあり、descriptor(sel)がフォルトなしに読めるとき 1 になる値で、LAR と LSL が読む前に確認するものです。gdtrとidtrは GDT と IDT のレジスターで、SGDT がストアするとおり、ベースアドレスをビット 79:16 に、リミットをビット 15:0 に持ちます。ldtrとtrは LDTR と TR の中のセレクターで、LDT とタスクステートセグメントのものです。LGDT、LIDT、LLDT、LTR がこれらに代入します。set_descriptor(sel, d)- セレクターが指す GDT または LDT のエントリに 8 バイトの
dを書き込みます。たとえば LTR はこれでタスクステートセグメントのディスクリプターをビジーにします。 interrupt(n)- 例外が配送されるのと同じようにベクター n のハンドラーをそのゲートを通して呼び出しますが、エラーコードはありません。64 ビットモードでは、ハンドラーのコードセグメントを確認します。より特権の高いハンドラーには、TSS がその特権レベルに対して与えるスタック、またはゲートが指定する TSS の IST エントリが与えられます。SS、RSP、RFLAGS、CS、次の命令のアドレスをプッシュし、TF、NT、RF をクリアし、割り込みゲートを通る場合は IF もクリアします。テストはそこで止まり、プローブが記録するとおり、#BP のようなそのベクターの例外で終わります。そのケースは Linux のプロセスとして実行され、テストはそのプロセスから見える Linux のテーブルを使います。DPL 3 を持つのはベクター 3、4、0x80 のゲートだけで、0x33、0x23、0x2b はユーザープログラムの 64 ビットと 32 ビットのコードセグメント、およびデータセグメントです。
load(a, 64),store(a, 64, v),dest.address- アドレスにあるメモリで、ここではその 64 ビット分です。スタック、ストリング命令のメモリ、BT のオペランドの先にあるビットに使います。
dest.addressはメモリオペランドの場所です。ストアはその後のロードから見えます。これはストリング移動のソースとデスティネーションが重なる場合に意味を持ちます。 canonical(a),writable(a),readable(a)- アドレスがカノニカルかどうか。ビット 63:47 がすべて等しいこと、または CR4.LA57 が有効にする 5 レベルページングではビット 63:56 がすべて等しいことです。また、アドレス a への書き込み、または読み取りが成功するかどうかです。
io_allowed(p, 8),io_read(p, 8),io_write(p, 8, v)- IN、OUT、INS、OUTS の I/O ポートで、0 から FFFFH までであり、メモリではありません。ここではポート
pの 8 ビット、またはpから上のポートの 16 ビットか 32 ビットです。io_allowedは、タスクステートセグメントの I/O 許可ビットマップがそれらのポートのビットをクリアしているかどうかを示し、命令がこれを確認するのは CPL が IOPL より大きいときだけです。io_readはポートが返す値を返し、io_writeはポートに書き込みます。デバイスは読み取りのたびに別の値を返すことがあり、読み取りや書き込みがそれ以上の動作をすることもあります。 r = cpuid_leaf(leaf, sub),r[0],cpuid_faulting- リーフとサブリーフに対する CPUID へのプロセッサーの応答。
r[0]からr[3]は EAX、EBX、ECX、EDX に返す 32 ビットの値で、サブリーフのないリーフはsubを無視します。応答はプロセッサー自身のもので、ハイパーバイザーの下ではハイパーバイザーのものなので、テストはすべてのプロセッサーに共通する動作だけを確認します。4 つの 32 ビット値が返り、ほかには何も変わらないことです。cpuid_faultingは、オペレーティングシステムが CPL 0 以外での CPUID に #GP を発生させるようにしているとき 1 です。 tsc(),tsc_aux,pru(n)tsc()はタイムスタンプカウンターです。64 ビットで、プロセッサーのリセットから独自の速さで数えます (ハイパーバイザーの下では、ハイパーバイザーがオフセットとスケールを適用したとおりです)。tsc_auxは TSC_AUX レジスターの 32 ビットで、オペレーティングシステムが CPU ごとに設定します (Linux は CPU の番号に、そのノードの番号かける 4096 を足した値にします)。pru(n)は RDPRU がnに対して読むレジスターで、0 なら MPERF、1 なら APERF です。これらの値はプロセッサーや時間が決めるものです。テストは記録したケースが書き込んだ値からそれらを取り戻し、RAX と RDX のビット 63:32 がクリアされていることなど、残りを確認します。random_ready(),random(n),seed_ready(),seed(n)random_ready()は RDRAND の背後にある乱数生成器が命令に渡す数を用意できているかどうか (1 または 0) で、random(n)はその数のnビットです。seed_ready()とseed(n)は RDSEED の背後にある生成器について同じものです。数はランダムなので、テストはそれらと、用意できていたかどうかを、記録したケースのデスティネーションと CF から取り戻し、残りを確認します。os_timeout(t)- UMWAIT または TPAUSE の待機は、イベントがそれより早く終わらせない限り、タイムスタンプカウンターが
tに達するまで続きます。その待機がオペレーティングシステムの上限が先に尽きたために終わったとき 1、そうでなければ 0 です。tsc()と同じく、時間が決めるものです。 mxcsr,mxcsr_maskmxcsrは SSE と AVX の浮動小数点命令の制御およびステータスレジスターである MXCSR です。mxcsr_maskは、FXSAVE がストアするとおりの、プロセッサーがサポートするそのビットで、Intel のプロセッサーでは FFFFH、Zen 5 では 2FFFFH で、そのビット 17 は AMD のアラインされていないオペランドの例外のマスクです。xmm[i],ymm[i],zmm[i],opmask[i]- 128、256、または 512 ビットとしてのベクトルレジスター
iと、マスクレジスターi(k0 から k7) を、それらをまとめて保存および読み込む命令が扱うのと同じように番号で指定したもの。xmm[i] = vはレガシ SSE 命令と同じようにビット 127:0 を書き込み、ほかのビットを保持します。zmm[i] = vは 512 ビットすべてを書き込みます。ymm[i].dq[1]は、下で説明する要素ビューで読むとおり、ビット 255:128 です。 xcr0,xss,xinusexcr0とxssは XCR0 と IA32_XSS レジスターで、オペレーティングシステムが XSAVE ファミリに管理させる状態コンポーネント (x87、SSE、AVX、AVX-512 の 3 つ、PKRU … で、スーパーバイザーのものは IA32_XSS) を示します。xinuseは XINUSE、つまり初期構成にない状態コンポーネントで、XGETBV が ECX = 1 で読むとおりです。MXCSR が 1F80H でないときは、SSE もその中に入ります。xsave_offset(i, xcomp)- ヘッダーの XCOMP_BV が
xcompである XSAVE 領域の中で、状態コンポーネントi(2 以上) がある位置。ビット 63 がクリア (標準形式) なら、CPUID リーフ 0DH が与えるオフセットにあります。セット (コンパクト形式) なら、バイト 576 から始まるxcompのうちそれより下のコンポーネントの後にあり、各コンポーネントは CPUID が示す大きさで、CPUID が求める場合は 64 バイト境界に置かれます。 fsbase,gsbase,pkrufsbaseとgsbaseは FS と GS のベースアドレスで、FS または GS プレフィックスがアドレスに加える値です。pkruは PKRU で、保護キーごとのユーザーページへのアクセス権で、キー k について、ビット 2k がセットされているとすべてのアクセスを、ビット 2k + 1 がセットされていると書き込みを拒否します。msr[n],msr_exists(n),msr_allows(n, v)- RDMSR と WRMSR が ECX で受け取るとおりの番号で指定した 64 ビットのモデル固有レジスター
n。msr[n] = vはそれに書き込みます。プロセッサーごとに独自のセットがあります。msr_existsはレジスターnを持つかどうかを、msr_allowsはそのレジスターが値vを取れるかどうかを示します。vはプロセッサーがそのレジスターで予約しているビットをセットしてはならず、レジスターがアドレスを保持する場合はカノニカルでなければなりません。FS と GS のベースはレジスター C000_0100H と C000_0101H です。プローブのケースは Linux のプロセスとして実行され、その EFER は D01H (ロングモード、SYSCALL、実行不可ページが有効) で、KVM のゲストである Zen 5 では SVME もセットされており、KVM はそれをセットしたままにします。ユーザーモードではこれらを読めないため、プローブが記録したフォルトからテストが推定した値です。 efer,star,lstar,cstar,fmask,kernel_gs_base,sysenter_cs- 名前で指定したモデル固有レジスター。
eferは EFER (C000_0080H) で、そのビット 0 の SCE が SYSCALL を有効にします。star、lstar、cstar、fmaskは STAR、LSTAR、CSTAR、SFMASK (C000_0081H から C000_0084H) で、SYSCALL のセレクター、64 ビットモードと互換モードのエントリポイント、および SYSCALL がクリアするフラグです。kernel_gs_baseは KernelGSbase (C000_0102H) で、SWAPGS が GS のベースと交換します。sysenter_csは SYSENTER_CS で、sysenter_espとsysenter_eipとともに (174H から 176H)、SYSENTER のセレクター、スタック、エントリポイントです。 pmc(n),pmc_exists(n)- RDPMC が
nに対して読むパフォーマンスモニタリングカウンターと、プロセッサーがそれを持つかどうか。カウンターの値は、タイムスタンプカウンターと同じくプロセッサーが決めるもので、テストは記録したケースが書き込んだ値からそれを取り戻します。 enqueue(a, v),mcommit_ok()enqueue(a, v)は ENQCMD による、アドレスaのデバイスレジスターへの 64 バイトのコマンドvのストアです。デバイスが受け付けると 1 です。再試行を求めたとき、またはaがそのようなレジスターではないとき (通常のメモリを含みます) は 0 で、ストアはそれを元のままにします。mcommit_ok()は MCOMMIT より前のすべてのストアがエラーなしにメモリに到達したかどうかで、これはプラットフォームの応答です。smm,smm_restore()smmは SMI が入るシステムマネジメントモードでは 1 です。smm_restore()は RSM による SMM からの復帰で、SMI が SMRAM に保存したレジスター、RIP、RFLAGS を読み戻し、そのモードを終えます。ssp,u_cet,s_cet,pl0_sspsspは CET のシャドウスタックポインターです。u_cetとs_cetはモデル固有レジスター IA32_U_CET (6A0H) と IA32_S_CET (6A2H) で、それぞれ CPL 3 とそれより下で CET の各部分を有効にします。ビット 0 がシャドウスタック、1 が WRSS、2 が間接分岐追跡、10 が SUPPRESS、11 が TRACKER で、TRACKER は間接 CALL や JMP がセットし ENDBR64 がクリアします。pl0_sspは IA32_PL0_SSP (6A4H) で、CPL 0 のシャドウスタックポインターです。cr4のビット 23 である CR4.CET が CET 全体を有効にします。ss_load(a, 64),ss_store(a, 64, v),ss_store_user(a, 64, v)- シャドウスタック上のロードとストアで、シャドウスタックの命令と制御転送だけが行います。
aのページが、CPL 3 ではユーザーモードの、それより下ではスーパーバイザーモードの、WRUSS のss_store_userではユーザーモードのシャドウスタックページでない限り、#PF を発生させます。 uif,uintr_tt,uintr_misc,send_ipi(v, id)uifはユーザー割り込みを受け入れるユーザー割り込みフラグです。uintr_ttは IA32_UINTR_TT (985H) で、ユーザー割り込みターゲットテーブルのアドレスで、有効な場合はビット 0 がセットされます。uintr_miscは IA32_UINTR_MISC (986H) で、そのビット 31:0 がテーブルの最大インデックスです。send_ipi(v, id)は、APIC ID がidのプロセッサーに送る、ベクターvの通常のプロセッサー間割り込みです。rtm_active,rtm_nest,rtm_nest_max,ldtrk_suspended,hle_active,fallbackrtm_activeはプロセッサーが RTM のトランザクションを実行中かどうか、rtm_nestは XBEGIN がどれだけ深くネストしているか、rtm_nest_maxはネストをどれだけ深く許すか (プロセッサー独自の上限) です。ldtrk_suspendedは XSUSLDTRK がロードをトランザクションの読み取りセットから外しているかどうか、hle_activeは HLE の領域を実行中かどうか、fallbackはアボートがどこへ行くかです。tx_abort(status),tx_commit()tx_abort(status)はアボートです。最も外側の XBEGIN 以降のすべてのレジスターとメモリへの書き込みが取り消され、EAX がstatusになり、プロセッサーはfallbackから実行を続けます。tx_commit()は最も外側の XEND がコミットするかどうかで、これはプロセッサーが決めることです。別のプロセッサーがトランザクションのメモリに書き込んでいることがあるからです。iwkey,wrap_key(key, meta),unwrap_key(h)iwkeyは Key Locker の内部ラッピング鍵で、ソフトウェアは読み込ませることはできても読み取ることはできません。ビット 255:0 が暗号化鍵、383:256 が完全性の鍵、384 が NoBackup、388:385 が KeySource です。wrap_key(key, meta)は、ENCODEKEY128 と ENCODEKEY256 がその鍵で AES-GCM-SIV を使って AES の鍵から作るもので、128 ビットの完全性タグと、その上に暗号化された鍵が並びます。unwrap_key(h)はその逆で、AESENC128KL とその仲間が受け取るものです。ハンドルhが保持する鍵 (メタデータ、続いてwrap_keyが作ったもの) で、別の鍵で作られたハンドルや、作られた後に変更されたハンドルのように、hが完全性のテストに失敗した場合は -1 です。どちらの結果もプロセッサーが決めるものです。ケースは鍵を知りえず、手元のどのプロセッサーも Key Locker を持たず、アルゴリズムのモデルを確かめられないため、テストはそれらを計算せずに各ケースから取ります。rtit_ctl,rtit_status,ptw_packet(v, 64, ip)- Intel PT の制御レジスターとステータスレジスターである IA32_RTIT_CTL (570H) と IA32_RTIT_STATUS (571H)、および PTWRITE がトレースに書き込む、
vをペイロードとする PTW パケットです。ipが 1 の場合は、その後に命令のアドレスを持つ FUP パケットが続きます。 bnd,bnd.number- MPX のバウンドレジスター BND0 から BND3 で、128 ビットです。下限はビット 63:0、上限はビット 127:64 にあり、BNDMK は上限を 1 の補数として保持するので、すべてゼロのレジスターはすべてのアドレスを許します。
.numberは命令がエンコードする番号で、最大 15 です。ブロックは BND4 から BND15 を拒否します (#UD)。 mib.address,base_reg(x),index_reg(x)- BNDLDX と BNDSTX のメモリオペランドは読み取られません。そのアドレス、つまりベースレジスターとディスプレースメントの和 (ベースレジスターがなければ 0) はポインターのアドレスで、バウンドテーブルのエントリを選び、インデックスレジスターはポインターの値を保持します。
base_reg(x)とindex_reg(x)は、そのようなオペランド、または BNDMK のオペランドのベースレジスターとインデックスレジスターの値で、持たないものは 0 です。 bndcfgu,bndcfgs,bndstatus,bound_fault(s)bndcfguは CPL 3 での MPX の構成 BNDCFGU、bndcfgsはそれより下での構成である MSR IA32_BNDCFGS です。ビット 0 が MPX を有効にし、ビット 63:12 がバウンドディレクトリのアドレスを保持します。bndstatusは BNDSTATUS で、MPX が最後に #BR を発生させた理由を示し、bound_fault(s)は BNDSTATUS をsにセットした後に #BR を発生させます。ブロックの書き込みのうち、フォルトの後まで残るのはこれだけです。MPX が無効なとき、および MPX を持たないすべてのプロセッサーでは、MPX の命令は何もしません。key_loaded- VIA のプロセッサーでの RFLAGS のビット 30。PadLock の AES エンジンが前の REP XCRYPT の制御ワードと鍵を保持しているとき 1 で、その場合次の REP XCRYPT はそれらを再び読み込みません。RFLAGS のストアやロード (PUSHF、POPF、割り込み) はすべてこれをクリアし、REP XSHA1 と REP XSHA256 もクリアします。
ace_load(c, k),ace_cw,ace_defined(),ace_encrypt(b)- PadLock の AES エンジン。
ace_loadはアドレスcから制御ワードを読み込みます。ビット 3:0 がラウンド数 (0 は 16)、ビット 4 がすべてのブロックを 1 か所に出力すること (MAC)、ビット 5 が任意のアラインメントのデータ、ビット 6 がアルゴリズム (0 が AES)、ビット 7 がメモリからの鍵、ビット 8 が中間結果、ビット 9 が復号、ビット 11:10 が鍵のサイズです。また、ラウンド鍵を 16 個読み込みます。エンジンはそれをkにある 128 ビットの鍵から展開するか、そこから読み取ります。ace_cwはエンジンが保持する制御ワードで、ace_defined()は VIA が結果を未定義としている場合に 0 です。ace_encryptとace_decryptは、エンジンの鍵を使って、ブロックに FIPS-197 の暗号、またはその等価逆暗号を適用します。 rng_msr,sha1_block(h, w),sha256_block(h, w)rng_msrは PadLock の乱数生成器を有効にし (ビット 6)、そのビット 31:5 を XSTORE が返す MSR 110B です。sha1_block(h, w)とsha256_block(h, w)はそのハッシュエンジンの 1 ステップで、64 バイトのブロックwを処理した後の SHA-1 または SHA-256 の状態hです。エンジンはhをプロセッサーのバイト順のダブルワードとしてメモリに保持し、SHA はwのワードをビッグエンディアンで読みます。lwp_cbaddr,lwp_cfg,lwp_count[i],lwp_head,lwp_min(i)- AMD の Lightweight Profiling。
lwp_cbaddrは使用中の制御ブロックのアドレス (MSR LWP_CBADDR、LWP が無効な間は 0) です。lwp_cfgはオペレーティングシステムが許す機能で、制御ブロックの Flags のビットにあり、ビット 39:32 にはこのコアの番号があります (MSR LWP_CFG)。lwp_count[i]とlwp_headはイベントiのカウンターと、次のレコードが入るリングバッファー内のオフセットで、LWP は実行中これらを内部に保持し、求められたときに制御ブロックに書き込みます。lwp_min(i)は、プロセッサーがイベントiに許す最小の間隔です。 ptsc(),this_ripptsc()は Performance Time Stamp Counter で、LWP のレコードが持つことのある、プロセッサーの 100 MHz のクロックです。this_ripは命令自身のアドレスで、これも LWP のレコードが持ちます。ripは次の命令のアドレスで、this_ripに命令の長さを足したものです。
仮想化 (VMX、SVM、SEV-SNP、Intel TDX) とエンクレーブのページでは、プロセッサーのモードとハイパーバイザーの構造体が加わります。その手順は長いため、ブロックは以下のように各ステップに名前を付け、ステップが何を確認し何を読み込むかを挙げたマニュアルの節を示します。
in_vmx,vmx_nonroot,seam,in_smm,in_smx- プロセッサーが VMX 動作 (VMX operation) 中 (VMXON と VMXOFF の間)、ゲストの中 (VMX non-root operation、つまり VMX 非ルート動作)、Intel TDX のセキュアアービトレーションモード (SEAM、そのゲストはトラストドメインです)、システムマネジメントモード、SMX 動作中 (GETSEC[SENTER] の後) であるとき 1、そうでなければ 0。プローブが実行される Linux のプロセスは、どれにも該当しません。
dual_monitor,mov_ss- SMI と SMM のデュアルモニター処理 (dual-monitor treatment) が有効なとき 1、および命令が SS への MOV または SS の POP の直後にあるとき 1。後者は 1 命令の間イベントをブロックします。
current_vmcs,vmxon_ptr,NO_VMCS,maxphyaddrcurrent_vmcsはゲストを記述する構造体である現在の VMCS の物理アドレス、vmxon_ptrは VMXON が受け取った領域の物理アドレスです。NO_VMCSはすべて 1 で、現在の VMCS がないときの値です。maxphyaddrは物理アドレスの幅で、命令はアドレスをこれと照らして確認します。phys_read(a, 32),phys_write(a, 64, v)- 物理アドレスにあるメモリで、ハイパーバイザーの構造体が使い、どのリニアアドレスからも届かないものです。ここではその 32 ビットと 64 ビットです。
vmcs_read(p, f),vmcs_write(p, f, v),vmcs_has(f)pにある VMCS のフィールドf。VMREAD が受け取るエンコーディングで指定し、そのビット 14:13 が幅 (16、64、32 ビット、またはナチュラル幅) を、ビット 0 が 64 ビットフィールドのビット 63:32 を選ぶことを示します。また、プロセッサーがそのフィールドを持つかどうかです。プロセッサーは VMCS のデータを独自の形式で保持するため、フィールドは位置ではなく名前で指定します。launched(p),vmcs_clear(p),set_launched(p)- VMCS のローンチ状態で、VMLAUNCH の後は 1、VMCLEAR の後は 0 です。VMCLEAR は VMCS をクリア状態にし、プロセッサーが保持する VMCS のデータのコピーを領域に書き込ませます。
IA32_VMX_BASIC,IA32_FEATURE_CONTROL- マニュアルでの名前で表した、
msr[...]が読むモデル固有レジスターの番号。VMX の機能レジスターはプロセッサーが何をサポートするかを示します。たとえば IA32_VMX_BASIC のビット 30:0 にある VMCS リビジョン識別子です。 vm_succeed(),vm_fail(n),vm_fail_invalid()- VMX 命令が結果を報告する方法。成功では CF、PF、AF、ZF、SF、OF をクリアします。現在の VMCS がある場合の失敗では ZF をセットし、エラー番号
nを VMCS の VM 命令エラーフィールドに書き込みます。現在の VMCS がない場合の失敗では CF をセットします (Intel SDM の Volume 3、33.2 と 33.4)。 vm_exit(21)- ゲストの中で実行された命令が、その基本理由 (ここでは VMPTRLD のもの) の VM exit で、ブロックが示す場合は exit qualification とともに、ハイパーバイザーに制御を渡します。テストはゲストと同じくそこで止まります。
controls_ok(),host_state_ok(),guest_state_ok(),msr_load_ok()- VM entry が、VMX 制御 (29.2.1)、ホスト状態領域 (29.2.2 と 29.2.3)、ゲスト状態領域 (29.3.1) のチェックを通過するかどうか、および VM-entry MSR-load 領域の MSR を読み込むかどうか (29.4)。プロセッサーはこれら何百ものチェックを独自の順序で行うため、テストはその結果をケースから取ります。
load_guest(),entry_fail(33)- VM entry は現在の VMCS のゲスト状態領域を読み込みます (29.3.2)。CR0、CR3、CR4、DR7、RSP、RIP、RFLAGS、隠れた部分を含むセグメントレジスター、GDTR、IDTR、および制御が指定する MSR です。CPL はゲストの SS の DPL になります。最初のチェックの後で失敗した VM entry (29.8) は、ビット 31 をセットした exit reason を記録し、代わりに VM exit と同じようにホスト状態領域を読み込みます (30.5)。RFLAGS はビット 1 を除いてクリアされます。
exit_controls_ok(),eptp_ok(v)- VM-exit 制御が、VMCALL がデュアルモニター処理を有効にする前に行うチェックを通過するかどうか (34.15.6.1)、および
vが VM entry の受け付ける EPT ポインターであるかどうか (29.2.1.1)。IA32_VMX_EPT_VPID_CAP が許すメモリタイプとページウォークを持ち、予約済みビットがセットされていないことです。 gif,intercepted(0x80),vm_exit(0x80)gifは AMD のグローバル割り込みフラグで、STGI がセットし CLGI がクリアします。intercepted(0x80)は、SVM のゲストで、そのハイパーバイザーがその exit コード (ここでは VMRUN のもの) のイベントをインターセプトするかどうかで、その場合命令はその #VMEXIT で終わります。save_host(a),vmcb_ok(),set_rflags(v),set_cpl(n)- VMRUN は、ホストに戻る #VMEXIT のために、ホストの状態をプロセッサー独自の形式で VM_HSAVE_PA が示すアドレスに保存します。VMCB の中のゲストの状態を確認し (AMD APM の Volume 2、15.5.1。テストはその結果をケースから取ります)、RFLAGS と CPL を、ゲストの状態の残りとともに VMCB のオフセットから読み込みます。
vmcb_save_segments(a),vmcb_load_segments(a),init_state()- ディスクリプターが読み込んだ属性、リミット、ベースを伴う FS、GS、LDTR、TR で、それぞれ 16 バイトずつ VMCB の 440H、450H、470H、490H にあります。また、INIT シグナルが残す状態で、SKINIT はそこからセキュアローダーを開始します。
snp_active,asid,vmplsnp_activeは SEV-SNP の SNP が有効なゲストの中では 1 です。asidは実行中のゲストの ASID で、ハイパーバイザーでは 0 です。vmplはその VM 許可レベルで、0 が最も特権が高いレベルです。guest_pa(va),system_pa(gpa),npt_large(gpa)- 仮想アドレスに対する、ゲストのページテーブルによるゲスト物理アドレス (マップがなければ #PF)、およびそれに対する、ハイパーバイザーのネストされたページテーブルによるシステム物理アドレス。後者は 2 MB のページでマップしていることがあります (マップがなければ #VMEXIT(NPF)、400H)。
rmp(spa),set_rmp(spa, v),in_rmp(spa)- SEV-SNP のリバースマップテーブルの中のページのエントリ。APM はその形式をプロセッサーに任せているため、モデルの数値として表します。ビット 63:0 がゲスト物理アドレス、64 が Assigned、72 が 2 MB のページ、80 が Immutable、127:96 が ASID (RMPREAD がストアするレイアウト)、128 が Validated、129 が VMSA で、ビット 136 から上に各 VMPL の 8 ビットの許可マスクが続きます。また、RMP_BASE から RMP_END までのテーブルがそのページのエントリを持つかどうかです。
seam_loader,seam_ready_ok(),seam_call(loader)- Intel TDX のモジュールは SEAM ルート動作で実行され、
seam_loaderが 1 の場合はそのローダーとして実行されます。SEAMCALL は準備ができていればそこに入ります。SEAM コールは SMM VM exit と同じように動作します。ハイパーバイザーの状態は SEAM 転送 VMCS に保存され、その VMCS が現在の VMCS になり、モジュールの状態が読み込まれます。 leaf_exists(n),leaf_function(n)- GETSEC、ENCLS、ENCLU、ENCLV、SEAMOPS、PCONFIG は、EAX が選ぶリーフを実行し、マニュアルはそれをリーフごとに説明しています。プロセッサーがリーフ
nを持つかどうかと、リーフの処理で、後者は報告するコードを返し、0 が成功です。テストはリーフが書き込むものをケースから取ります。 smx_capabilities(i),seamops_capabilities(),pconfig_target(t)- プロセッサーの応答。
smx_capabilities(i)は GETSEC[CAPABILITIES] がインデックスiに対して返すもの、seamops_capabilities()はプロセッサーが持つ SEAMOPS のリーフのビットマップ、pconfig_target(t)は CPUID リーフ 1BH が PCONFIG のターゲットtを挙げているかどうかで、1 が TME-MK、2 が TSE です。 enclave_mode,VCenclave_modeはプロセッサーが SGX エンクレーブの中で実行している間は 1 です。VCは SEV のゲストの VMM 通信例外 #VC です。
値は任意のサイズの整数で、レジスターとメモリは符号なし数として読みます。書き込みは下位ビットを保持するので、-1 はすべて 1 になります。ブロックの中では、レジスターとフラグは命令の前の値を保ち、書き込みは命令の終わりに順に反映されます。XADD EAX, EAX のように、あるオペランドが別のオペランドと同じレジスターを指す場合、どちらも元の値を読み、最後の書き込みが残ります。これが読み手にとって問題にならないように、レジスターに書き込んだ後でそれを読むブロックはありません。
ベクトルのページのブロックは、データフロー図を描くモデルから書いており、以下を加えます。
zmm1,zmm2,src3,mem- 構文の中の位置で表したオペランドで、それぞれそのブロックの命令形式がその位置に持つ最も広いレジスターにちなんで名付けています。
zmm1は、命令形式が使うものに応じて xmm1、ymm1、zmm1 のどれかで、mm1は MMX レジスターです。ある命令形式ではレジスター、別の命令形式ではメモリであるオペランドはsrc2またはsrc3(最初の位置ではdest) で、常にメモリであるものはmemです。k1とk2はマスクレジスターです。 .b,.w,.d,.q,.dq,.qq- 8、16、32、64、128、または 256 ビットの要素の配列としてのオペランドで、ビット 0 から数えます。
zmm2.d[3]はビット 127:96 です。.sb、.sw、.sd、.sqは同じビットを符号付き数として読みます。メモリでは、.d[i]はオペランドのアドレスから 4i バイトの位置です。 k1[i],zeroing- 書き込みマスクのビット i で、要素 i が書き込まれるかどうかを示します。マスクのない命令形式ではすべての要素について 1 です。マスクされた要素は値を保持するか、
zeroingが真である{z}形式では 0 になります。その要素はメモリからも読み取られないため、読み取りはif k1[i]:の内側に置かれます。 k1.group[1],zmm2.group[j]- 1 つのオペランドが表す、連続するレジスターで、構文では
+を付けて書きます。k1+1はマスクレジスターのペア、zmm2+3は 4 つのベクトルレジスターです。グループはエンコードされたレジスターの番号の下位 1 ビット、または下位 2 ビットをクリアした番号から始まります。したがってk1.group[0]はペアの偶数番のレジスターで、k1.group[1]はその次の奇数番のレジスター、zmm2.group[j]は 4 つのうちの j 番目のレジスターです。 VL- 命令形式のビット単位のベクトル長。128、256、または 512 で、MMX では 64 です。複数の長さを扱うブロックは要素数を
VL // 32のように数えます。 m32bcst- ブロードキャスト。メモリ上の 1 つのダブルワードがすべての要素を表すので、
src3.d[i]はどの i についてもそのダブルワードです。 mem.base,mem.index,mem.scale,load(a, 32)- ギャザーまたはスキャッターのメモリオペランド。ベースアドレス、符号付きオフセットのベクトルレジスター、およびオフセットにかけるスケールです。
load(a, 32)はアドレス a の 32 ビットを読み、store(a, 32, v)は命令の終わりに順にそれを書き込むので、1 つのアドレスへの 2 つのストアのうち後のものが残ります。k1.write(0)は、ギャザーとスキャッターが行うように、マスクレジスター全体をクリアします。 src1 = xmm1.read()- デスティネーションがソースでもあるレガシ形式のための、命令の前の状態のレジスターのコピー。ブロックは
xmm1に書き込み、元の要素をsrc1から読みます。ブロックが要素ごとに書き込むメモリも、ブロックの終わりに書き込まれます。マスクされていない例外 (#XM) のようにフォルトしたベクトル命令は、レジスターとメモリを元のままにします。 ssat(x, 16),usat(x, 8)- そのビット数の符号付きまたは符号なしの範囲に飽和させた
x。rol、popcount、ternlogなど、要素演算のほかのヘルパーは、計算する内容にちなんで名付けています。 sub_bytes(s),shift_rows(s),mix_columns(s),sub_word(w)- FIPS-197 が定義する AES のラウンドの各ステップで、バイト j が列 j // 4 の行 j % 4 にある 128 ビットの状態
sに対して行います。すべてのバイトを S-box に通すこと、行 r を r バイト左に回転すること、各列を GF(2^8) 上の多項式として 3x^3 + x^2 + x + 2 をかけ、x^4 + 1 を法とすることです。inv_mix_columns(s)のように前にinv_が付くと、ステップを元に戻します。sub_word(w)は、鍵拡張の SubWord と同じように、ダブルワードの 4 バイトを S-box に通します。 aes_encrypt(s, k, 128),aes_decrypt(s, k, 256)- 暗号全体で、そのすべてのラウンドです。128 ビットのブロック
sを、そのビット数の鍵kで暗号化または復号します。AES-128 では 10 ラウンド、AES-256 では 14 ラウンドで、FIPS-197 の鍵拡張によるラウンド鍵を使います。鍵のバイトは、XMM レジスターが保持するとおりのメモリの順序です。 gf2p8inv(x)- AES と GFNI の体である GF(2^8) におけるバイト
xの逆元で、0 に対しては 0 です。この体のバイトは x^8 + x^4 + x^3 + x + 1 を法とする多項式です。S-box はバイトをその逆元に移し、さらにアフィン写像に通します。 choose(x, y, z),majority(x, y, z)- FIPS 180-4 が Ch と Maj と呼ぶ SHA のビット単位の関数。
xが 1 の位置ではyのビット、0 の位置ではzのビットを取るものと、3 つのビットの多数決です。SHA-1 はこれらをラウンド 0 から 19 と 40 から 59 で使い、SM3 はラウンド 16 以降で使います。 sum0(x, 32),sum1,sigma0,sigma1- FIPS 180-4 がシグマで表す関数で、大文字はラウンド用、小文字はメッセージスケジュール用であり、32 ビット (SHA-256) または 64 ビット (SHA-512) のワードに対して働きます。
xを 3 つの量だけ右に回転するか、2 つの量だけ右に回転して 3 つ目の量だけ右にシフトし、3 つを加えます (排他的論理和)。SHA-256 では 2、13、22 (sum0)、6、11、25 (sum1)、7 と 18 の回転と 3 のシフト (sigma0)、17 と 19 の回転と 10 のシフト (sigma1) です。SHA-512 では同じ順に、28、34、39、次に 14、18、41、次に 1 と 8 の回転と 7 のシフト、最後に 19 と 61 の回転と 6 のシフトです。 sm3_p0(x),sm3_p1(x)- SM3 の置換 P0 と P1 (GB/T 32905)。
x ^ rol(x, 9, 32) ^ rol(x, 17, 32)と、15 と 23 を使った同じ式です。 sm4_sub_word(x),sm4_l(x),sm4_l_key(x)- SM4 のステップ (GB/T 32907)。ダブルワード
xの各バイトをその S-box に通すことで、S-box はバイトをアフィン写像に通し、x^8 + x^7 + x^6 + x^5 + x^4 + x^2 + 1 を法とする GF(2^8) における逆元に移し、再びアフィン写像に通します。また、その線形写像で、ラウンドではxと、xを 2、10、18、24 ビット左に回転したものを加え、鍵拡張では 13 と 23 ビットで同様にします。 hmac_sha256(k, m, n),gcm_encrypt(k, iv, p, n),gcm_tag(k, iv, a, na, c, nc)- PBNDKB の暗号処理。32 バイトの鍵
kによる、mのnバイトに対する SHA-256 を使った HMAC (RFC 2104)。そして Galois/Counter Mode の AES-256 (NIST SP 800-38D) で、pのnバイトを鍵kと 12 バイトの IVivで暗号化し、aのnaバイトと暗号文cのncバイトを 16 バイトのタグで認証します。鍵、データ、結果は、loadが読むとおりのメモリの順序のバイトです。 platform_key- プロセッサーが内部に保持し、どの命令も読めない 256 ビットの鍵で、PBNDKB はここから暗号化に使う鍵を導出します。
ブロックの最後の行は、命令形式が書き込むビットより上のデスティネーションレジスターのビットがどうなるかを示します。VEX 形式と EVEX 形式はそれらをゼロにし、レガシ SSE 形式は元のままにし、MMX 形式はそのレジスターが共有する x87 の状態を変更します。
浮動小数点の要素は数値であり、以下のヘルパーで計算します。
.f32,.f64,.f16,.bf16- 単精度、倍精度、半精度、bfloat16 の数値としてのオペランドの要素。要素を移動するだけの命令は、そのビットである
.dや.qを使います。 add(a, b),sub,mul,div,sqrt(a)- 正確な結果を、要素の形式に 1 回だけ丸めたもの。MXCSR.RC の指定どおり、または命令形式の
{er}の指定どおりに丸めます。 fmin(a, b),fmax(a, b)- MINPS と MAXPS が選ぶとおりの、2 つのうち小さいほうまたは大きいほう。どちらかが NaN であるか、両方がゼロのときは
bです。 fmadd(a, b, c),fmsub,fnmadd,fnmsuba * b + c、a * b - c、-(a * b) + c、-(a * b) - cを 1 回だけ丸めたもの。fcmp(imm8, a, b),comi(a, b),ucomi(a, b)- CMPPS の述語 imm8 & 31 による比較で、真または偽。また COMISS と UCOMISS の順序で、0 が大きい、1 が小さい、2 が等しい、3 が順序なし (unordered) です。
to_f32(x),cvt_int(a, 32),cvtt_int(a, 32)- 変換。別の形式の要素または整数からの変換と、丸めまたは切り捨てによる 32 ビット整数への変換で、値が収まらない場合は整数の不定値 (integer indefinite)、つまり最小の符号付き整数になります。
cvt_uintは符号なし整数に変換し、収まらない場合はすべて 1 になります。to_f16(a, imm8)は imm8 の指定どおりに丸め、to_bf16_ne(a)は BF16 命令と同じように丸めます。つまり最近接偶数への丸めで、デノーマルはゼロにフラッシュし、フラグはセットしません。fmadd_ne(a, b, c)がaかけるbに単精度のcを足した値を丸める方法も同じで、bfloat16 の要素、または VDPPHPS では半精度の要素に対して使い、後者ではデノーマルを保持します。to_f32_ne(a)は半精度または bfloat16 の要素を正確に、フラグなしで変換し、to_f32_f16c(a)は VCVTPH2PS と同じように半精度を変換します。正確に変換し、デノーマルは DAZ の指定にかかわらず DE なしで保持し、SNaN は IE とともにクワイエット化します。 to_bf8(a),to_hf8(a),to_hf8s(a)- AVX10.2 の 8 ビット形式への変換。E5M2 (
.bf8、IEEE 754 の無限大と NaN を持ちます) と E4M3 (.hf8、最大値 448、無限大はなく、符号ごとに 1 つの NaN を持ち、それはすべて 1 です) で、最近接偶数に丸め、デノーマルは保持します。丸めた後に収まらない値、または無限大は、E5M2 の無限大または E4M3 の NaN になります。to_bf8sとto_hf8sは代わりにその符号の最大の数に飽和させ、to_hf8_oddは奇数への丸めを行い (ACE の VCVTROPS2HF8)、単精度のデノーマルはゼロとして扱います。to_bf4s(a)は 4 ビットの E2M1 (.bf4、1 バイトに 2 つ) に変換します。E2M1 には無限大も NaN もなく、収まらない値と NaN はその符号の最大の数 6 になります。to_bf6s(a)とto_hf6s(a)は同様に ACE の 6 ビットの E3M2 (.bf6、最大値 28) と E2M3 (.hf6、最大値 7.5) に変換し、その要素 i はビット 6i+5:6i で、隙間なく詰めます。これらの変換、および 8、6、4 ビットの形式からの正確な変換は、MXCSR を使わず、フラグもセットしません。 round(a, imm8),rndscale(a, imm8),reduce(a, imm8)- imm8 が指定する丸めで整数値に丸めた
a、imm8[7:4] ビットの小数部に丸めたa、およびその丸めで残る部分、つまりaから丸めた値を引いたもの。 getexp(a),scalef(a, b),fpclass(imm8, a)- 数値としての
aの指数 floor(log2(|a|))、aに 2 の floor(b) 乗をかけて丸めたもの、およびaが imm8 で選ぶクラスのどれかに属するかどうか。ビット 0 が QNaN、1 が +0、2 が -0、3 が +inf、4 が -inf、5 がデノーマル、6 が負の有限数、7 が SNaN です。 getmant(a, imm8),frange(a, b, imm8),fixupimm(a, b, sc, imm8)- imm8[1:0] が指定する区間にスケールした
aの仮数。aとb、またはその絶対値のうち小さいほうまたは大きいほうに、imm8[3:2] が選ぶ符号を付けたもの (VRANGEPS)。そして VFIXUPIMMPS の修正で、表scがbのクラス (NaN、ゼロ、+1、無限大、負の数、正の数) ごとに結果を指定し、選択肢にはa自身も含まれます。 fminmax(a, b, imm8),comx(a, b),cvts_int(a, 8),cvtts_int(a, 32)- AVX10.2 の IEEE 754-2019 の最小値と最大値で、imm8 が選ぶ形のものに imm8[3:2] が選ぶ符号を付けたもの。COMISS の比較で、VCOMXSS はその結果を符号付き比較のフラグにも変換します。そして飽和する、丸めまたは切り捨てによる整数への変換で、収まる最も近い整数になり、NaN は 0 になります。
rcp(a),rsqrt(a),rcp14(a),rsqrt14(a),rcp28(a),exp2(a)- 1/a、1/sqrt(a)、2^a の推定値で、最後の数ビットはプロセッサーによって異なります。RCPPS と RSQRTPS (およびそれぞれの形式の VRCPPH、VRCPBF16)、VRCP14PS、AVX512ER の VRCP28PS と VEXP2PS です。ブロックは正確な値を示し、テストはマニュアルが許す相対誤差の範囲内の結果をすべて受け入れます。その相対誤差はブロックに記しており、RCPPS では 1.5 * 2^-12、VRCP14PS では 2^-14 です。その横には、そのページの Zen 5 で記録した結果の数と、その中の最悪の誤差を示しており、テストはケースがそれを守ることを確認します。正規化数には小さすぎる結果は、RCPPS が常にそうするように、命令がそれをフラッシュする場合はゼロになることがあります。ゼロ、無限大、NaN、負の数の平方根は正確な結果になり、例外を発生させるのは AVX512ER の推定だけです。
NaN、デノーマル、例外は、MXCSR の DAZ と FTZ を含め、SSE の規則に従います。要素の例外は、すべての要素を計算した後で通知されます。マスクされていない例外は #XM を発生させて命令は何も書き込まず、マスクされた例外は MXCSR のフラグをセットします。{er} と {sae} はそれらを抑制し、複素数の FP16 乗算は、SDM が述べるとおり、すべての例外がマスクされているかのように動作します。手元のどのプロセッサーも AVX512-FP16 を持たないため、これは確認できていません。BF16 の要素 (.bf16) に対する算術は、代わりに BF16 命令の規則に従います。最近接偶数に丸め、デノーマルはゼロとして扱い、デノーマルの結果はフラッシュし、フラグはセットせず、MXCSR を無視します。
AMD の 3DNow! のページは MMX レジスターの中の 2 つの単精度数で計算し、そのヘルパーは名前はそのままですが、AMD のマニュアルが示すとおりの 3DNow! の規則に従います。指数が 0 の数は小数部にかかわらずゼロなので、デノーマルはありません。指数が 255 の数はサポートされず、それに対する演算は UNDEFINED です。ただし、ゼロにそのような要素を足すとその要素になるように、AMD のその命令の表が別の結果を示している場合は除きます。結果は最近接に丸め、同値の場合は偶数に丸めます。2^-126 より小さい正確な結果はゼロになり、丸めた後に 2^128 以上になる結果は最大の数になります。無限大や NaN がないためです。正確にゼロになる和は最初の項の符号を取り、2 つのゼロの和は両方が負のときだけ負になります。例外を発生させたり MXCSR に触れたりするものはありません。手元のどのプロセッサーも 3DNow! を持たないため、これらのブロックは AMD のドキュメントと手で求めたケースに基づいています。
add(a, b),sub,mul,fmin,fmax,comi(a, b),is_unsupported(x)- 上と同じ算術。
fminとfmaxはゼロを +0 とみなし、ゼロに対しては +0 を返します。comiは 0 が大きい、1 が小さい、2 が等しい (どの 2 つのゼロも等しくなります)、3 が要素の指数が 255 の場合で、これはis_unsupportedがテストします。 cvtts_int(a, 32),to_f32(n)- PF2ID と PF2IW による整数への変換で、切り捨て、32 ビットまたは 16 ビットに飽和させます。PI2FD による整数からの変換で、丸めではなく切り捨てます。
rcp(a),rsqrt(a)- PFRCP と PFRSQRT の推定値。1/a を 2^-14 以内で、
aの符号を付けた 1/sqrt(|a|) を 2^-15 以内で求め、これは AMD が示す範囲です。ゼロの推定値はその符号の最大の数です。 rcp_step(a, b),rsqrt_step(a, b),refine(t, x)- 1/b または 1/sqrt(b) の推定値 x を 24 ビットにまで高める、Newton-Raphson 法の 2 つのステップ。PFRCPIT1 は 2 - b * x を計算し (
rcp_step)、PFRSQIT1 は b と x の 2 乗から (3 - b * x * x) / 2 を計算します (rsqrt_step)。どちらも 32 ビットで計算し、PFRCPIT2 だけが読む形で要素に詰めます。整数ビットの後の 8 ビットは、x が目標に近いときはすべて等しいため、省かれます。PFRCPIT2 (refine) はそれらを戻し、x をかけます。AMD はその積を、説明していない補正の後で丸めるため、テストは正確な積から最後の桁の 1 単位以内にある任意の単精度数を受け入れます。
x87 のページは浮動小数点ユニットを加えます。それぞれが明示的な整数ビットを持つ 80 ビットの拡張倍精度の数を保持する 8 つのレジスターのスタックと、そのワード群です。
st0…st7,st[i]- スタックのレジスター ST(0) から ST(7) で、命令の前のスタックの先頭から数えます。構文の ST(i) は、ほかのオペランドと同じく
destまたはsrcです。 push(v),pop()- プッシュは先頭の下に
vを書き込み、それを先頭にします。ポップは ST(0) を解放し、先頭を 1 つ上に移します。すべての書き込みと同じく、これらはブロックの終わりに反映されるので、st1は ST(1) だったレジスターを指したままです。ブロックがプッシュの前にst0に代入したものは ST(1) に入ります。 empty(r),free(r)- レジスターが空とタグ付けされているかどうかと、FFREE のようにそうタグ付けすること。値はレジスターに残ります。
underflow(),overflow()- スタックフォルト。空のレジスターオペランド、または満杯のスタックへのプッシュです。どちらも IE と SF をセットし、アンダーフローでは C1 = 0、オーバーフローでは 1 です。IE がマスクされている場合に続く処理はブロック自身のコードで、通常は QNaN の浮動小数点不定値である
INDEFINITEの書き込みです。 top,fcw,fsw,ftw- TOP と、制御ワード、ステータスワード、タグワード。ステータスワードの ES と B は、マスクがクリアされている例外フラグがセットされているときに限りセットされます。タグワードは FNSTENV がストアするとおりに読み、各レジスターのタグはその内容から求めます。
fip,fcs,fop,fdp,fds- 制御命令ではない最後の x87 命令の位置。そのオフセットとコードセグメント、オペコード、およびメモリオペランドのオフセットとセグメントで、FNSTENV と FNSAVE がストアし、FLDENV と FRSTOR が読み込みます。
c0…c3,ie,de,ze,oe,ue,pe,stack_fault- 条件コード、例外フラグ、および SF (
sfは RFLAGS のフラグです)。ヘルパーが発生させる例外は代入しません。テストは条件コードを XED の記録と照らし合わせます。XED の記録は命令が条件コードを変更するか未定義のままにするかだけを示すので、FABS の C1 のように条件コードをクリアするブロックは「changed」に該当します。 add(a, b),sub,mul,div,sqrt(a)- ベクトルのブロックと同じ名前で、同じ意味です。正確な結果を 1 回だけ丸めます。ベクトルのブロックは MXCSR に従って丸め、x87 のブロックは制御ワードの PC (仮数を 24、53、または 64 ビットに、指数はレジスターの範囲のまま) と RC に従って丸めます。丸めによって絶対値が大きくなったとき C1 は 1 になり、そうでなければ 0 です。メモリオペランドはその幅の数 (m32fp は単精度、m64fp は倍精度) で、FIADD の
signed(src)のような整数はその正確な値です。 to_f80(x),to_f32(x),cvt_int(x, 16),to_bcd(x),from_bcd(v)- 変換。ロードは正確です。単精度 (
to_f32) や倍精度 (to_f64) へのストアは PC ではなく RC に従って丸めます。整数へのストアは RC に従って、またはゼロ方向に (cvtt_int、FISTTP) 丸めます。収まらない値は整数の不定値、つまり最小の整数になります。to_bcdは FBSTP がストアするとおり 10 進 18 桁に丸め、from_bcdはそれを読みます。 comi(a, b),ucomi(a, b),is_nan(x)- FCOM と FUCOM の比較。0 が大きい、1 が小さい、2 が等しい、3 が順序なしで、IE はそれぞれ、どの NaN に対しても、または SNaN に対してだけ発生します。
is_nan、is_inf、is_zero、is_denormal、is_finite、is_unsupportedは数のクラスを返します。 less(a, b),abs(x)- 数
aがbより小さいかどうか (どちらかが NaN なら偽) と、FABS のように符号ビットをクリアしたx。どちらも何も発生させません。 round(x),scale(a, b),exponent(x),significand(x)- RC に従って整数に丸めた
x(FRNDINT)、aに 2 の (ゼロ方向に切り捨てたb) 乗をかけたもの (FSCALE)、および FXTRACT がxを分ける 2 つの部分で、数値としての指数と、指数を 0 にしたxです。 prem(a, b),prem1(a, b),r.quotient,r.partialaをbで割った剰余、つまりaからbの整数q倍を引いたもので、正確に求めます。qは切り捨て (FPREM)、または最も近い整数に丸めたもので、同値の場合は偶数です (FPREM1)。.quotientは符号を除いたqで、その下位ビットが C0、C3、C1 に入ります。.partialはaとbの指数が 64 以上離れているとき 1 で、その場合 1 回のステップは指数を 32 から 63 だけ減らします。sin(x),cos,tan,atan2(y, x),exp2m1(x),ylog2(y, x),ylog2p1(y, x)- 超越関数命令の関数。正弦、余弦、正接、点 (x, y) の角度、2^x - 1、y * log2(x)、y * log2(x + 1) で、それぞれ PC にかかわらず RC に従って 64 ビットに 1 回だけ丸めます。計算するすべての結果について、正確な結果であっても PE を発生させます。正弦、余弦、正接は x * pi / Pi に対するもので、Pi はプロセッサーが引数を簡約するのに使う pi の 66 ビットの近似値です。pi / 2 の倍数の近くでは、結果はわずかに異なる角度のものになります。
次の例外があります。
- IE: SNaN のオペランド、387 で廃止されたエンコーディング (アンノーマル、疑似 NaN、疑似無限大)、またはゼロかける無限大のような無効な演算
- DE: デノーマルのオペランド
- ZE: ゼロによる除算
- OE、UE、PE: 丸めた結果が大きすぎる、小さすぎる、または不正確
マスクされた例外はそのフラグをセットするだけです。マスクされていない例外は ES と B もセットし、ケースが記録するとおり、次の待機型の命令が #MF を発生させます。マスクされていない例外の 2 つの種類は、異なる終わり方をします。
- 演算の前に検出されるもの (IE、スタックフォルト、DE、ZE): 演算はそれを検出したヘルパーで止まります。ブロックがその呼び出しの後でレジスター、TOP、メモリに書き込むものは実行されないので、結果は書き込まれず、ポップもされません。それでもステータスは書き込まれます。フラグ、条件コード (FCOM の順序なし)、RFLAGS (FCOMI のもの) です。止まるヘルパーは何も丸めないので、それがセットする C1 は 0 です。ロードの DE はこの規則の例外で、Zen 5 はそれでもデノーマルを読み込みます。
- レジスターへのオーバーフローまたはアンダーフロー: 結果は、その指数を 2^24576 によって範囲内に戻して書き込まれます。メモリへの場合は何も書き込まれません。
例外が保留された状態で始まる待機型の命令は、何よりも先に #MF を発生させます。
超越関数命令は、最後のビットがプロセッサーによって異なる近似です。その疑似コードは 1 回だけ丸めた正確な値を示し、テストはプロセッサーが記録した結果を、最近接への丸めでは正確な値から 1 ulp 以内、ほかのモードでは 1.5 ulp 以内であれば受け入れます。これは Intel のマニュアルが示す範囲です。C1 はプロセッサーが自身の近似値をどちらの方向に丸めたかを示すので、結果が正確な値から 4 分の 1 ulp 以内にある場合は、どちらを示すこともあります。
AMX と ACE のページはタイルを加えます。最大で 64 バイトの行を 16 行まで持つ 8 つのレジスターと、それぞれの形を与える TILECFG です。AMX のパレット 1 では、各タイルは LDTILECFG が読み込んだ行数と 1 行あたりのバイト数を持ちます。ACE のパレット 2 では、すべてのタイルが 64 バイトの行を 16 行すべて持ちます。手元のどのプロセッサーもどちらも持たないため、これらのブロックは実行していません。
tmm1,tmm2,tmm[i]- 構文のタイルで、ベクトルのオペランドと同じく構文の中の位置で名付けたもの、および番号で指定したタイル
i。 tmm1.rows,tmm1.colsb- タイルの行数と、その各行のバイト数。構成が省いたタイルでは 0 と 0 で、そのタイルは有効ではありません。
tmm1.row[r],tmm1.row[m].f32[n]- タイルの行
r(512 ビット) と、ベクトルのページと同じビューによるその要素。書き込みは命令の終わりに反映されます。そのときタイルはその行数より先がゼロにされ、書き込まれた各行は 1 行あたりのバイト数より先がゼロにされます。ブロックの最後の行がそのことを示しています。 tilecfg,palette,start_row- STTILECFG がストアする 64 バイトとしての TILECFG。バイト 0 にパレット、バイト 1 に
start_row、続いて各タイルの 1 行あたりのバイト数 (バイト 16 + 2n) と行数 (バイト 48 + n) があります。パレット 0 は構成が読み込まれていないことを意味します。start_rowは中断された TILELOADD または TILESTORED が再開する位置です。 palettes,xfd- プロセッサーが持つパレット (パレット p にビット p) と IA32_XFD。IA32_XFD のビット 18 によって、オペレーティングシステムはスレッドにタイルを使わせないようにできます (#NM)。
bsr0- ACE のブロックスケールレジスター。1 バイトずつの 128 個のスケールで、行の A スケールがバイト 64 から 127、列の B スケールがバイト 0 から 63 にあります。スケール e は 2^(e - 127) を表し、FFH は NaN です。
mem.address,mem.stride- TILELOADD または TILESTORED のメモリの行 0 の位置 (ベースとディスプレースメントの和) と、行の間隔 (インデックスレジスターかけるスケール、インデックスレジスターがなければ 0)。
add_ne(a, b),neg(x)- 2 つの単精度数の和で、
fmadd_neと同じく、最近接偶数に丸め、入力と出力のデノーマルをフラッシュし、フラグはセットしません。また、符号を反転したxです。 mul_exact(a, b),add_exact(x, y),round_ftz(x, e)- 要素の正確な積と和、および正確な値に 2^e をかけて単精度に 1 回だけ、最近接偶数に丸めたもの。BF16 と単精度のデノーマルはゼロで、FP16 と FP8 のデノーマルは数として扱います。NaN、ゼロかける無限大、両方の符号の無限大は、QNaN の不定値 FFC00000H になります。正規化された単精度数には小さすぎる結果はゼロ、大きすぎる結果は無限大になります。
to_f16_ne(a),cvt_f32_ne(x)- 単精度数を最近接偶数に丸めて FP16 に変換したもので、単精度のデノーマルはゼロとして扱い、FP16 のデノーマルは保持します。また、整数を最近接偶数に丸めて単精度に変換したものです。どちらも MXCSR を使わず、フラグもセットしません。
オペランド
各ページは、XED が記録するとおりに、命令形式が何を読み何を書き込むかを挙げています。明示的なオペランドは構文のオペランドで、構文の順序どおりです。暗黙のオペランドはオペコードで固定され構文からは省かれるもので、CMPXCHG のアキュムレーター、フラグレジスター、スタックなどです。オペランドサイズやベクトル長だけが異なる命令形式は 1 つのブロックを共有し、ブロックは各オペランドのサイズ (r8/16/32/64) やレジスター (xmm, ymm, zmm) を示します。
r/m8,xmm/m128- ほかは同じであるレジスター形式とメモリ形式を、Intel のマニュアルと同じように 1 つにまとめて書いたもの。
- read, write
- 命令形式がオペランドを読む (read)、書き込む (write)、またはその両方を行います。
- conditional write, conditional read
- 命令形式が一部の場合にだけオペランドを書き込む、または読みます。CMPXCHG は比較が失敗したときだけアキュムレーターに読み込み、カウントが 0 の REP ストリング命令はメモリに触れません。
- (masked),
{k} - マスクレジスターに従って書き込まれる EVEX のデスティネーション (masked) と、マスクレジスターそのもの。マスクが除外した要素は値を保持する (その場合デスティネーションも読み取られます) か、
{z}があればクリアされます。VBLENDMPS などのブレンド命令は、代わりにマスクレジスターをセレクターとして使い、各要素をどちらかのソースから選びます。 - push, pop, pop twice
- 命令形式が x87 のレジスタースタックに値をプッシュする (push)、または 1 つ (pop) か 2 つ (pop twice) の値をポップし、その先頭を移動します。
- address only
- メモリオペランドのアドレスだけを計算し、LEA のようにメモリにはアクセスしません。
stack,rSP- プッシュはスタックポインターの下に書き込み、ポップはスタックポインターの位置から読みます。どちらもスタックポインターを移動します。
m8 at ES:[rDI]- ストリング命令のように、命令形式が角かっこの中のレジスターでアドレスを指定するメモリ。ES は固定です。デフォルトの DS は、セグメントプレフィックスで置き換えられるため書いていません。
- (NF=0)
- NF が省略可能な APX 形式は、NF=0 のときだけフラグを書き込みます。
フラグ
表には、命令形式がテストまたは変更するフラグごとに列があります。ステータスフラグ OF、SF、ZF、AF、PF、CF、命令形式が影響する場合は RFLAGS のその他のフラグ、そして x87 のステータスワードの条件コード C0 から C3 です。
T- テスト (Tested)。条件ジャンプのように、命令形式がフラグを読みます。
M- 変更 (Modified)。結果に応じてセットまたはクリアされます。
0,1- 結果にかかわらずクリアまたはセットされます。
U- 未定義 (Undefined)。命令形式はフラグを変更しますが、その値に依存してはなりません。
P,A- スタックから (POPF、IRET)、または AH から (SAHF) 読み込まれます。
TM- ADC と RCL が CF に対して行うように、テストされた後に変更されます。
命令形式が複数の形でフラグに影響する場合は、When 列がどの場合かを示します。即値によるシフトまたはローテートでは、それはカウントが 1 か 2 以上かです。OF はカウントが 1 のときだけ定義され、カウント 0 はどのフラグも変更しないからです。カウントは、プロセッサーがそれを 5 ビット (64 ビットオペランドでは 6 ビット) にマスクした後に残る値です。NF が省略可能な APX 形式では NF=0 で、CMOVcc のように複数の条件を持つページでは、命令形式がフラグをテストする各条件です。「In some cases」は、カウントが 0 のときの CL によるシフトのように、命令形式がフラグを変更しない場合があることを意味します。
命令のフラグについて Intel のドキュメントが XED と異なることを述べている場合、表の下、または XED がフラグを記録していないことを示す行の下の注が、その違いを指摘します。そのセクション自体は XED のデータのままです。
例外クラス
例外クラスは、命令形式が従う例外条件のセットに対する XED の名前です。各プロセッサーモードで、#UD、#GP、#PF などのどの例外を、いつ発生させうるかを表します。ほとんどの名前は Intel のマニュアルの例外タイプに従っています。SSE_TYPE_2 は SSE 命令の Exceptions Type 2、avx-type-2 はその VEX 形式の同じタイプ、AVX512-E2 は EVEX のクラス E2 です。AMX や APX などのほかの拡張には独自のクラスがあります。汎用命令のほとんどは XED でクラスを持ちません。
各クラスは専用のページにリンクしており、そのページはプロセッサーモードごとの例外と、それぞれを発生させる原因、および XED がそのクラスに入れている命令を挙げています。例外クラスの索引にそのすべてを挙げています。
属性
XED が命令形式に付ける属性のうち、ページのほかの部分が示さないものをページに表示しています。
- privileged: CPL 0 only
- オペレーティングシステムのカーネルのように、命令形式は最高の特権レベルでのみ実行されます。
- not in real-address mode
- LTR のようなプロテクトモードの命令と同じく、命令形式はリアルアドレスモードでは無効です。
- accepts a LOCK prefix
- メモリ形式は LOCK プレフィックスを付けることができ、それによってリードモディファイライトがアトミックになります。LOCK 付きの命令形式は別に挙げています。
- locked: atomic read-modify-write
- 命令形式はアトミックです。LOCK プレフィックスを持つか、常にロックされるメモリとの XCHG です。
- always atomic
- AADD のように、命令形式は LOCK プレフィックスなしでアトミックです。
- accepts XACQUIRE, accepts XRELEASE
- 命令形式はハードウェアロックエリジョン (HLE) のヒントプレフィックスを付けることができます。
- repeated: count in rCX
- REP 形式。rCX をゼロまで減らしながら操作を繰り返します。REPE と REPNE は ZF でも止まります。
- aligned memory operand
- メモリオペランドはアラインされていなければならず、そうでなければ命令形式は例外を発生させます。128 ビットの SSE オペランドと FXSAVE では 16 バイト、VMOVAPS と非テンポラルなロードおよびストアではオペランドのサイズ、XSAVE と MOVDIR64B では 64 バイトにアラインする必要があります。
- 4-byte aligned memory operand, 8-byte aligned memory operand
- XED は、メモリオペランドがオペランドサイズによる自然なアラインメントを必要とすると記録しています。アラインされていないとき #GP を発生させる AADD などの RAO-INT 命令と、Intel のマニュアルがそのような規則を示していない CMPccXADD です (CMPccXADD のページに詳しく書いています)。
- non-temporal hint
- データはすぐには再利用されないと見込まれるので、プロセッサーはキャッシュを迂回できます。
- memory operand only names cache lines
- プリフェッチまたはキャッシュライン命令。メモリオペランドは操作の対象となるキャッシュラインを選び、データはレジスターに届きません。
- gather, scatter
- 命令形式は、インデックスのベクトル (
vm32x) から求めたそれぞれのアドレスで各要素をロードまたはストアします。 - write masking
- EVEX 形式は、マスクレジスター k1 から k7 でマスクできます。
- opmask selects the source
- VBLENDMPS のように、マスクレジスターは書き込みマスクではなく、各要素のソースを選びます。
- embedded broadcast (tuple Full)
- メモリ形式は 1 つの要素をロードしてすべての位置で使えます (
m32bcst)。タプルタイプ Full、Half、Quarter は、8 ビットのディスプレースメントのスケールのしかたを決めます。 - memory fault suppression
- マスクが除外した要素はメモリフォルトを発生させません。CFCMOVcc は条件が偽のときにメモリフォルトを発生させません。
- follows MXCSR
- MXCSR の丸め制御と例外マスクが命令形式に適用され、発生した浮動小数点例外は MXCSR のフラグをセットします。
{er}または{sae}を持つ命令形式は、丸めを上書きしたり、例外を抑制したりできます。 - always rounds to nearest even, denormal inputs read as zero, denormal results flushed to zero
- 命令形式は、MXCSR の指定にかかわらず、このように丸める (常に最近接偶数)、またはデノーマルの数を扱います (入力のデノーマルはゼロとして読み、結果のデノーマルはゼロにフラッシュする)。
- far transfer, indirect branch
- 分岐は rIP だけでなく CS も読み込む (far transfer)、または分岐先をレジスターかメモリから取ります (indirect branch)。
- may abort a TSX transaction
- Intel TSX のトランザクション領域の中で、命令形式は一部のプロセッサー、またはすべてのプロセッサーでトランザクションをアボートさせることがあります。「in some cases」はオペランドによって決まることを示し、たとえば CLD と STD は DF を変更するときだけアボートさせます。