x86 命令の例外クラス
ベクトル命令の多くは、例外に関する規則を他の多くの命令と共有しています。Intel のマニュアルはこれらの規則を例外クラスにまとめており、このリファレンスの各命令形式は属するクラスを示しています。
命令は完了せずに例外で止まることがあります。プロセッサーまたはオペレーティングシステムがその命令を許可していない場合は #UD、オペレーティングシステムが浮動小数点レジスターとベクトルレジスターを実行中のタスクにまだ切り替えていない場合 (CR0.TS がセットされている場合) は #NM、メモリオペランドがセグメントの外にある、アラインされていない、またはマップされていない場合は #SS、#GP、#PF、アラインメントチェックがアラインされていないアクセスを捕らえた場合は #AC、浮動小数点のエラーでは #XM または #MF です。命令がこれらのうちどれを、どのプロセッサーモードで発生させうるかは、多数の命令からなるグループ単位で共通です。Intel のマニュアルは各グループを例外クラスとして一度だけ説明し、命令のページはそれを参照しています。
Intel XED はすべての命令形式のクラスを記録しています。以下の各クラスには、プロセッサーモードごとの条件を独自の言葉で説明し、XED がそのクラスに入れている命令を挙げたページがあります。
クラスのページの読み方
- プロセッサーモード
- リアルアドレスモード、仮想 8086 モード、プロテクトモード (互換モード、つまり 64 ビットのオペレーティングシステム上の 32 ビットコードを含む)、64 ビットモード
- レガシ、VEX、EVEX
- マニュアルの Exceptions Type 1 から 12 は、命令のレガシ SSE エンコーディングと VEX エンコーディングを 1 つの表で説明しています。XED は 2 つを SSE_TYPE_2 と avx-type-2 のように別々に名付けており、これらのページも同様です。VEX または EVEX エンコードされた命令はリアルアドレスモードと仮想 8086 モードでは常に #UD を発生させるため、それ以外の条件が意味を持つのはプロテクトモードと 64 ビットモードだけです。マニュアルの表がほかの 2 つのモードにも印を付けている場合でも同じです。
- #XM ではなく #UD
- マスクされていない SIMD 浮動小数点例外が #XM を発生させるのは、オペレーティングシステムが #XM を処理することを示すために
CR4.OSXMMEXCPTをセットしている場合だけです。そうでなければ、命令は #UD を発生させます。 - フォルト抑制
- EVEX エンコードされた命令のほとんどのクラスは、マスクレジスターが無効にした要素のメモリフォルトを抑制します。#SS、#GP、#PF を発生させうるのは有効な要素だけです。名前が NF で終わるクラスには、このような抑制はありません。
SSE
| クラス | 要約 | ニーモニック | 形式 |
|---|---|---|---|
| SSE_TYPE_1 | Legacy SSE moves that need a 16-byte aligned memory operand, such as MOVAPS and MOVNTDQ, which Intel's manual calls Exceptions Type 1. | 7 | 16 |
| SSE_TYPE_2 | Legacy SSE floating-point arithmetic on full 16-byte vectors, such as ADDPS, SQRTPD and CVTPS2DQ, which Intel's manual calls Exceptions Type 2. | 30 | 60 |
| SSE_TYPE_2D | The legacy SSE4.1 dot products DPPD and DPPS, which Intel's manual lists under Exceptions Type 2. | 2 | 4 |
| SSE_TYPE_3 | Legacy SSE floating-point arithmetic on scalars and other operands smaller than 16 bytes, such as ADDSS, COMISD and CVTSI2SD, which Intel's manual calls Exceptions Type 3. | 31 | 74 |
| SSE_TYPE_4 | Legacy SSE instructions with a 16-byte memory operand and no floating-point exceptions, such as PADDD, PSHUFB, ANDPS and AESENC, which Intel's manual calls Exceptions Type 4. | 139 | 274 |
| SSE_TYPE_4M | The legacy unaligned moves MOVUPS, MOVUPD and MOVDQU, which Intel's manual refers to Exceptions Type 4 but exempts from its alignment rule. | 3 | 12 |
| SSE_TYPE_5 | Legacy SSE moves, inserts, extracts and conversions on operands smaller than 16 bytes without floating-point exceptions, such as MOVD, PINSRW and PMOVZXBW, which Intel's manual calls Exceptions Type 5. | 36 | 83 |
| SSE_TYPE_7 | Legacy SSE instructions without a memory operand or floating-point exceptions, such as MOVMSKPS, PSLLDQ and the shifts by an immediate count, which Intel's manual calls Exceptions Type 7. | 15 | 23 |
AVX
| クラス | 要約 | ニーモニック | 形式 |
|---|---|---|---|
| avx-type-1 | VEX-encoded moves whose memory operand must be aligned to its full size, such as VMOVAPS and VMOVNTDQ, which Intel's manual calls Exceptions Type 1. | 7 | 32 |
| avx-type-2 | VEX-encoded floating-point arithmetic on full vectors, such as VADDPS, VSQRTPD and the FMA instructions, which Intel's manual calls Exceptions Type 2. | 66 | 264 |
| avx-type-2D | The VEX-encoded dot products VDPPD and VDPPS, which Intel's manual lists under Exceptions Type 2 with one more reason for #UD. | 2 | 6 |
| avx-type-3 | VEX-encoded floating-point arithmetic on scalars and other operands smaller than 16 bytes, such as VADDSS, VCOMISD and the scalar FMA instructions, which Intel's manual calls Exceptions Type 3. | 55 | 124 |
| avx-type-4 | VEX-encoded integer, logical, shuffle and cryptographic instructions without floating-point exceptions, such as VPADDD, VPSHUFB and VAESENC, which Intel's manual calls Exceptions Type 4. | 170 | 629 |
| avx-type-4M | The VEX-encoded unaligned moves VMOVUPS, VMOVUPD and VMOVDQU, which Intel's manual refers to Exceptions Type 4 with one more reason for #UD. | 3 | 24 |
| avx-type-5 | VEX-encoded moves, inserts, extracts and conversions on operands smaller than 16 bytes without floating-point exceptions, such as VMOVD, VPINSRB and VPMOVZXBW, which Intel's manual calls Exceptions Type 5. | 37 | 114 |
| avx-type-5L | VLDMXCSR, which loads the MXCSR register from memory, with the conditions of Exceptions Type 5 of Intel's manual and a #GP for reserved bits. | 1 | 1 |
| avx-type-6 | VEX-encoded instructions without a legacy SSE form, such as VBROADCASTSS, VINSERTF128, VPERM2I128 and VMASKMOVPS, which Intel's manual calls Exceptions Type 6. | 25 | 79 |
| avx-type-7 | VEX-encoded instructions without a memory operand or floating-point exceptions, such as VMOVMSKPS, VPSRLDQ and the shifts by an immediate count, which Intel's manual calls Exceptions Type 7. | 15 | 44 |
| avx-type-8 | VZEROALL and VZEROUPPER, which clear vector registers and take no operands, the class that Intel's manual calls Exceptions Type 8. | 2 | 2 |
| avx-type-11 | The F16C conversions VCVTPH2PS and VCVTPS2PH between half and single precision, which Intel's manual calls Exceptions Type 11. | 2 | 8 |
| avx-type-12 | The AVX2 gathers, such as VGATHERDPS and VPGATHERQQ, which load elements from the addresses in a vector of indices, the class that Intel's manual calls Exceptions Type 12. | 8 | 16 |
| avx-type-14 | CMPccXADD, which compares a value in memory and adds to it in one atomic step, the class that Intel's manual calls Exceptions Type 14. | 1 | 2 |
AVX-512
| クラス | 要約 | ニーモニック | 形式 |
|---|---|---|---|
| AVX512-E1 | The EVEX-encoded aligned moves VMOVAPS, VMOVAPD, VMOVDQA32 and VMOVDQA64, whose memory operand must be aligned to its full size, which Intel's manual calls Exceptions Type E1. | 4 | 36 |
| AVX512-E1NF | The EVEX-encoded non-temporal moves VMOVNTPS, VMOVNTPD, VMOVNTDQ and VMOVNTDQA, aligned and without fault suppression, which Intel's manual calls Exceptions Type E1NF. | 4 | 12 |
| AVX512-E2 | EVEX-encoded floating-point arithmetic on full vectors, such as VADDPS, VFMADD231PD and VCVTPS2DQ, with memory fault suppression, which Intel's manual calls Exceptions Type E2. | 173 | 992 |
| AVX512-E3 | EVEX-encoded floating-point arithmetic on scalars, such as VADDSS, VFMADD231SD and VCMPSD, with memory fault suppression, which Intel's manual calls Exceptions Type E3. | 93 | 186 |
| AVX512-E3NF | EVEX-encoded scalar floating-point compares and conversions without fault suppression, such as VCOMISS, VCVTSD2SI and VCVTSI2SS, which Intel's manual calls Exceptions Type E3NF. | 34 | 108 |
| AVX512-E4 | EVEX-encoded integer, logical and other instructions without floating-point exceptions, such as VPADDD, VPTERNLOGD and VMOVDQU32, with memory fault suppression, which Intel's manual calls Exceptions Type E4. | 254 | 1,520 |
| AVX512-E4NF | EVEX-encoded permutes, shuffles and other instructions without floating-point exceptions or fault suppression, such as VPERMD, VSHUFPS and VPUNPCKLDQ, which Intel's manual calls Exceptions Type E4NF. | 86 | 520 |
| AVX512-E5 | EVEX-encoded instructions that read part of a vector or a scalar from memory, such as VPMOVZXBD and VCVTDQ2PD, with memory fault suppression, which Intel's manual calls Exceptions Type E5. | 17 | 93 |
| AVX512-E5NF | The EVEX-encoded VMOVDDUP, which duplicates double-precision elements, without fault suppression, the one instruction of what Intel's manual calls Exceptions Type E5NF. | 1 | 6 |
| AVX512-E6 | EVEX-encoded broadcasts and down-converting stores, such as VBROADCASTSS and VPMOVDB, with memory fault suppression, which Intel's manual calls Exceptions Type E6. | 37 | 125 |
| AVX512-E6NF | EVEX-encoded extracts and inserts of 128- and 256-bit lanes, such as VEXTRACTF32X4 and VINSERTI64X4, without fault suppression, which Intel's manual calls Exceptions Type E6NF. | 37 | 111 |
| AVX512-E7NM | EVEX-encoded instructions without a memory operand, such as VPMOVM2D, VPMOVD2M and the broadcasts from a general-purpose register, which Intel's manual calls Exceptions Type E7NM. | 16 | 48 |
| AVX512-E7NM128 | The EVEX-encoded VMOVHLPS and VMOVLHPS, register moves that exist only as 128-bit forms, which Intel's manual calls Exceptions Type E7NM.128. | 2 | 2 |
| AVX512-E9NF | EVEX-encoded 128-bit moves, inserts and extracts of single elements, such as VMOVD, VPEXTRW and VINSERTPS, without fault suppression, which Intel's manual calls Exceptions Type E9NF. | 17 | 48 |
| AVX512-E10 | EVEX-encoded scalar instructions that ignore the vector length, such as VRCP14SS and VFPCLASSSH, with memory fault suppression, which Intel's manual calls Exceptions Type E10. | 13 | 26 |
| AVX512-E10NF | EVEX-encoded scalar instructions without floating-point exceptions or fault suppression, VCVTSI2SD and VCVTUSI2SD from 32-bit integers and VCOMISBF16, which Intel's manual calls Exceptions Type E10NF. | 3 | 6 |
| AVX512-E11 | The EVEX-encoded half-precision conversions VCVTPH2PS and VCVTPS2PH, with memory fault suppression, which Intel's manual calls Exceptions Type E11. | 2 | 12 |
| AVX512-E12 | The EVEX-encoded gathers and scatters, such as VGATHERDPS and VPSCATTERQQ, which Intel's manual calls Exceptions Type E12. | 16 | 48 |
| AVX512-E12NP | The gather and scatter prefetches of the Xeon Phi, such as VGATHERPF0DPS and VSCATTERPF1QPD, which cannot fault, the class that Intel's manual calls Exceptions Type E12NP. | 16 | 16 |
| AVX512-K20 | VEX-encoded instructions on opmask registers without a memory operand, such as KANDW, KORTESTQ and KSHIFTLD, which Intel's manual calls Exceptions Type K20. | 51 | 54 |
| AVX512-K21 | The VEX-encoded opmask moves KMOVB, KMOVW, KMOVD and KMOVQ in the forms that can address memory, which Intel's manual calls Exceptions Type K21. | 4 | 13 |
MMX
| クラス | 要約 | ニーモニック | 形式 |
|---|---|---|---|
| mmx-mem | MMX instructions on MMX registers and 8-byte memory operands, such as PADDB, PMADDWD and PSHUFW, which Intel's manual lists as SIMD/MMX instructions with a memory reference. | 71 | 133 |
| mmx-nomem | PEXTRW and PMOVMSKB with MMX registers, which have no memory operand, as Intel's manual lists them among the SIMD/MMX instructions without a memory reference. | 2 | 2 |
| mmx-nofp2 | The MMX moves MOVQ, MOVNTQ and MASKMOVQ, which raise no floating-point exceptions, as Intel's manual lists them among the legacy SIMD/MMX instructions without FP exception. | 3 | 10 |
| mmx-nofp | CVTPI2PD, which converts two integers from an MMX register or memory to double precision without floating-point exceptions, as Intel's manual lists it among the legacy SIMD/MMX instructions with XMM and without FP exception. | 1 | 2 |
| mmx-fp | The SSE conversions CVTPI2PS, CVTPS2PI and CVTTPS2PI between MMX and XMM registers, which can raise SIMD floating-point exceptions, as Intel's manual lists them among the legacy SIMD/MMX instructions with XMM and FP exception. | 3 | 6 |
| mmx-fp-16align | The SSE2 conversions CVTPD2PI and CVTTPD2PI from double precision to integers in an MMX register, which need an aligned 16-byte memory operand, as Intel's manual lists them among the legacy SIMD/MMX instructions with FP exception and 16-byte alignment. | 2 | 4 |
AMX
| クラス | 要約 | ニーモニック | 形式 |
|---|---|---|---|
| AMX-E1 | AMX-E1 is the class that Intel's table of AMX exception classes gives LDTILECFG: the invalid-opcode checks shared by all AMX instructions, a general-protection fault for a tile configuration the processor rejects, and the faults of reading the 64-byte configuration from memory. | 1 | 1 |
| AMX-E1-EVEX | AMX-E1-EVEX is the ISE's and the APX specification's class for LDTILECFG in its EVEX encoding: all of AMX-E1, plus invalid-opcode checks on the EVEX fields that the instruction leaves unused. | 1 | 1 |
| AMX-E2 | AMX-E2 is the class that Intel's table of AMX exception classes gives STTILECFG: the invalid-opcode checks shared by all AMX instructions and the faults of writing the 64-byte configuration to memory. | 1 | 1 |
| AMX-E2-EVEX | AMX-E2-EVEX is the ISE's and the APX specification's class for STTILECFG in its EVEX encoding: all of AMX-E2, plus invalid-opcode checks on the EVEX fields that the instruction leaves unused. | 1 | 1 |
| AMX-E3 | AMX-E3 is the class that Intel's table of AMX exception classes gives the tile loads and stores: the shared AMX checks, a configured and valid tile, SIB addressing, the faults of the memory rows and #NM when extended feature disable blocks the tile data. | 5 | 5 |
| AMX-E3-EVEX | AMX-E3-EVEX is the ISE's and the APX specification's class for the tile loads and stores in their EVEX encoding: all of AMX-E3, plus invalid-opcode checks on the EVEX fields they leave unused. | 5 | 5 |
| AMX-E4 | AMX-E4 is the class that Intel's table of AMX exception classes gives the tile matrix multiplications: the shared AMX checks, three distinct and valid tiles whose shapes fit a multiplication within the matrix unit's limits, and #NM when extended feature disable blocks the tile data. | 12 | 12 |
| AMX-E5 | AMX-E5 is the class that Intel's table of AMX exception classes gives TILEZERO: the shared AMX checks, a configured and valid destination tile, and #NM when extended feature disable blocks the tile data. | 1 | 1 |
| AMX-E6 | AMX-E6 is the class that Intel's table of AMX exception classes gives TILERELEASE, which only makes the checks shared by all AMX instructions. | 1 | 1 |
| AMX-E7-EVEX | AMX-E7-EVEX is the ISE's AMX exception class for the AMX-AVX512 instructions that move a tile row, selected by an immediate, into a ZMM register (converting it in the TCVTROW forms): the AMX and AVX-512 enabling checks, a configured source tile, fixed EVEX fields, and #NM from CR0.TS or extended feature disable. | 6 | 6 |
| AMX-E8-EVEX | AMX-E8-EVEX is the ISE's AMX exception class for the AMX-AVX512 instructions that move a tile row, selected by a general-purpose register, into a ZMM register: the checks of AMX-E7-EVEX, except that EVEX.vvvv names that register. | 6 | 6 |
ACE
| クラス | 要約 | ニーモニック | 形式 |
|---|---|---|---|
| ACE-E1 | ACE-E1 is the ACE specification's exception class for its tile moves with an immediate row or column number: the AMX, ACE and AVX-512 enabling checks, a configured and valid tile, fixed EVEX fields, and #NM from CR0.TS or extended feature disable. | 2 | 2 |
| ACE-E2 | ACE-E2 is the ACE specification's exception class for BSRMOVF, which loads the whole block scale register: the ACE enabling checks, a loaded tile configuration, bsr0 as the only destination, #NM from CR0.TS or extended feature disable, and the faults of an optional memory source. | 1 | 2 |
| ACE-E3 | ACE-E3 is the ACE specification's exception class for BSRMOVH and BSRMOVL, which move one half of the block scale register to or from a ZMM register or memory: the checks of ACE-E2 plus an unused EVEX.vvvv. | 2 | 8 |
| ACE-E4 | ACE-E4 is the ACE specification's exception class for the outer products, which accumulate the outer product of two ZMM registers into a tile: the ACE and AVX-512 enabling checks, a configured and valid tile, fixed EVEX fields, and #NM from CR0.TS or extended feature disable. | 10 | 10 |
| ACE-E5 | ACE-E5 is the ACE specification's exception class for BSRINIT, which resets the block scale register: the tile and block scale enabling checks, a loaded tile configuration, bsr0 as the only operand, and #NM when extended feature disable blocks the tile data. | 1 | 1 |
| ACE-E6 | ACE-E6 is the ACE specification's exception class for its tile moves with the row or column number in a general-purpose register: the checks of ACE-E1, except that EVEX.vvvv names that register. | 2 | 2 |
APX
| クラス | 要約 | ニーモニック | 形式 |
|---|---|---|---|
| APX-EVEX-BMI | APX-EVEX-BMI is the APX specification's exception class for the BMI1 and BMI2 instructions in their EVEX encoding, which APX adds so that they can use the registers R16 to R31 and, for some of them, leave the flags unchanged. | 13 | 76 |
| APX-EVEX-CCMP | APX-EVEX-CCMP is the APX specification's exception class for CCMPscc and CTESTscc, the conditional compare and test instructions that APX adds in EVEX map 4. | 2 | 20 |
| APX-EVEX-CET-WRSS | APX-EVEX-CET-WRSS is the APX specification's exception class for WRSSD and WRSSQ in their EVEX encoding, which write to the shadow stack of the current privilege level. | 2 | 2 |
| APX-EVEX-CET-WRUSS | APX-EVEX-CET-WRUSS is the APX specification's exception class for WRUSSD and WRUSSQ in their EVEX encoding, with which code at CPL 0 writes to a user shadow stack. | 2 | 2 |
| APX-EVEX-CFCMOV | APX-EVEX-CFCMOV is the APX specification's exception class for CFCMOVcc, the conditionally faulting CMOVcc of EVEX map 4, whose memory faults and debug exceptions occur only when the condition is true. | 1 | 5 |
| APX-EVEX-CMPCCXADD | APX-EVEX-CMPCCXADD is the APX specification's exception class for CMPccXADD in its EVEX encoding, which APX adds so that the instruction can use the registers R16 to R31. | 1 | 2 |
| APX-EVEX-ENQCMD | APX-EVEX-ENQCMD is the APX specification's exception class for ENQCMD and ENQCMDS in their EVEX encoding, which send a 64-byte command to a device's enqueue register. | 2 | 2 |
| APX-EVEX-INT | APX-EVEX-INT is the APX specification's exception class for the integer instructions that APX promotes from the legacy maps into EVEX map 4, for the registers R16 to R31, a new destination register (NDD), flag suppression (NF) and zero-upper forms (ZU). | 35 | 617 |
| APX-EVEX-INVEPT | APX-EVEX-INVEPT is the APX specification's exception class for INVEPT in its EVEX encoding, the VMX instruction that invalidates translations derived from extended page tables (EPT). | 1 | 1 |
| APX-EVEX-INVPCID | APX-EVEX-INVPCID is the APX specification's exception class for INVPCID in its EVEX encoding, which invalidates TLB entries by process-context identifier (PCID). | 1 | 1 |
| APX-EVEX-INVVPID | APX-EVEX-INVVPID is the APX specification's exception class for INVVPID in its EVEX encoding, the VMX instruction that invalidates translations by virtual-processor identifier (VPID). | 1 | 1 |
| APX-EVEX-KMOV | APX-EVEX-KMOV is the APX specification's exception class for KMOVB, KMOVW, KMOVD and KMOVQ in their EVEX encoding, which APX adds so that the moves between mask registers and general-purpose registers or memory can use R16 to R31. | 4 | 20 |
| APX-EVEX-MOVRS | APX-EVEX-MOVRS is the APX specification's exception class for MOVRS in its EVEX encoding, a load with a hint that other processors will read the same data. | 1 | 2 |
| APX-EVEX-PP2 | APX-EVEX-PP2 is the APX specification's exception class for PUSH2 and POP2, which push or pop two 64-bit registers at once, and for their forms with the balanced push-pop hint. | 4 | 4 |
| APX-EVEX-RAO-INT | APX-EVEX-RAO-INT is the APX specification's exception class for the remote atomic operations AADD, AAND, AOR and AXOR in their EVEX encoding, which APX adds so that they can use the registers R16 to R31. | 4 | 8 |
| APX-LEGACY-JMPABS | APX-LEGACY-JMPABS is the APX specification's exception class for JMPABS, the 64-bit absolute direct jump that APX encodes with a REX2 prefix in legacy map 0. | 1 | 1 |
MSR instructions
| クラス | 要約 | ニーモニック | 形式 |
|---|---|---|---|
| MSR-IMM-VEX | MSR-IMM-VEX is XED's name for the exceptions of the VEX-encoded forms of RDMSR and WRMSRNS that take the MSR address as an immediate, which Intel documents on the instruction pages rather than as a named class. | 2 | 2 |
| MSR-IMM-EVEX | MSR-IMM-EVEX is the APX specification's exception class for RDMSR and WRMSRNS with an immediate MSR address in their EVEX encoding, which lets the register operand be R16 to R31. | 2 | 2 |
| USER-MSR-LEGACY | USER-MSR-LEGACY is XED's name for the exceptions of URDMSR and UWRMSR with the MSR address in a register, which Intel documents on the instruction pages rather than as a named class. | 2 | 2 |
| USER-MSR-VEX | USER-MSR-VEX is XED's name for the exceptions of the VEX-encoded URDMSR and UWRMSR with an immediate MSR address, which Intel documents on the instruction pages rather than as a named class. | 2 | 2 |
| USER-MSR-EVEX | USER-MSR-EVEX is the APX specification's exception class for URDMSR and UWRMSR in their EVEX encoding, with the MSR address in a register or an immediate and the registers R16 to R31 available. | 2 | 4 |
Other legacy-encoded instructions
| クラス | 要約 | ニーモニック | 形式 |
|---|---|---|---|
| LEGACY-RAO-INT | LEGACY-RAO-INT is XED's name for the exceptions of the remote atomic operations AADD, AAND, AOR and AXOR in their legacy encoding, which the ISE lists on the instruction pages rather than as a named class. | 4 | 8 |
| LEGACY-MOVRS | LEGACY-MOVRS is the ISE's exception class Legacy-MOVRS of the MOVRS load in its legacy encoding: #UD outside 64-bit mode or with a LOCK or REP prefix, and the faults of an ordinary load. | 1 | 2 |
| LEGACY-PREFETCH | LEGACY-PREFETCH is XED's name for the exceptions of PREFETCHRST2, which the ISE lists on the instruction's page: #UD for a LOCK prefix, in every mode, and nothing else. | 1 | 1 |
出典
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026), Chapter 2: the exception classes of SSE, AVX and AVX-512 instructions
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026), Section 2.5: CR0.TS
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026), Sections 11.5.1 and 15.6.1: SIMD floating-point exceptions and masking
- Intel XED, the X86 Encoder Decoder