x86-64.net
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x86-64 最適化ガイド

x86-64 プロセッサーでコードを速くするもの、プロセッサーの仕組み、各マイクロアーキテクチャーが求めることを、独自の言葉で、すべての主張の横に出典を添えて説明します。

このガイドは、ベンダーの最適化マニュアル、ベンダーとは独立した測定、コンパイラーのモデルが各マイクロアーキテクチャーについて述べていることをまとめたものです。ページはデータとして管理しています。各記述は、出典となる文書、そのリビジョン、節を示す主張 (claim) であり、それが欠けた主張があるとサイトはビルドされません。主張の後に付く出典へのリンクは、ページ末尾の一覧にあるその出典の項目を指しています。その項目には、主張を照合したバージョンが記されています。

出典どうしが常に一致するとは限りません。ベンダーのマニュアルが、それ自体の中で、あるいは以前のマニュアルと矛盾することもあれば、測定で別の数値が得られることも、コンパイラーのモデルが古いコアを想定していることもあります。そのような場合は、どちらかを黙って選ぶのではなく、もう一方の出典が何と述べているかを、その出典へのリンクとともに注記として主張の後に示します。

出典から取り入れるのは事実だけです。Intel と AMD のマニュアル、および Agner Fog のマニュアルは複製も翻案も許されていないため、ここの文章はすべて新たに書いたものです。命令ごとのレイテンシは、オープンなライセンスで公開されている LLVM のスケジューリングモデルか測定から取っており、マニュアルの表から取ることはありません。

プロセッサーの仕組み

  • Front end: How x86-64 cores fetch and decode code: decoded-instruction caches, loop buffers, macro-fusion, prefixes, alignment and NOP padding, Intel and AMD compared. 40 件の主張、うち 10 件は出典が食い違う。
  • Out of order: How x86-64 cores run code out of order: renaming, zeroing idioms, move elimination, partial writes, ports, the reorder buffer and dependency chains. 38 件の主張、うち 4 件は出典が食い違う。
  • Branches: How x86-64 cores predict branches: direction and target, BTBs, return stacks, indirect jumps, misprediction costs, CMOV, inlining and code layout. 41 件の主張、うち 7 件は出典が食い違う。
  • Memory: How x86-64 cores use caches and memory: cache levels, alignment, store forwarding, 4K aliasing, TLBs, prefetching, non-temporal stores and false sharing. 43 件の主張、うち 3 件は出典が食い違う。
  • Vectors: Vector code on x86-64: SSE, AVX2 or AVX-512 per core, VZEROUPPER, masks, gathers and scatters, lane-crossing shuffles, reductions and denormals. 39 件の主張、うち 3 件は出典が食い違う。
  • Measuring: How to time code on x86-64: core and reference cycles, the TSC, RDTSC and fences, performance counters, top-down analysis, turbo and noise. 38 件の主張、うち 1 件は出典が食い違う。

マイクロアーキテクチャー

出典

  1. AMD: Software Optimization Guide for the AMD Zen5 Microarchitecture, 58455, revision 1.00, August 2024. The Wayback Machine’s copy of AMD’s ZIP, which holds the guide as a PDF and a spreadsheet of instruction latencies. Its printed page numbers are those of the PDF. SHA-256 a9a9e04d910bccec; all rights reserved; facts only.
  2. AMD: Software Optimization Guide for the AMD Zen4 Microarchitecture, 57647, revision 1.00, January 2023. The Wayback Machine’s copy of AMD’s ZIP, which holds the guide as a PDF and a spreadsheet of instruction latencies; amd.com no longer serves it. Its printed page numbers are those of the PDF. SHA-256 ddea915eec7a91e3; all rights reserved; facts only.
  3. AMD: Software Optimization Guide for AMD EPYC 7003 Processors, 56665, revision 3.00, November 2020. The Wayback Machine’s copy of AMD’s ZIP, which holds the guide for Zen 3 as a PDF and a spreadsheet of instruction latencies; amd.com no longer serves it. The guide speaks for all of Family 19h, as it was written before Zen 4 joined the family; AMD’s first copy, titled for Family 19h, has the same text. Citations give the page numbers printed on the pages, which from Chapter 1 on run four ahead of the PDF’s own. SHA-256 51f0b563d2fe2a70; all rights reserved; facts only.
  4. AMD: Software Optimization Guide for AMD Family 17h Models 30h and Greater Processors, 56305, revision 3.02, March 2020. The Wayback Machine’s copy of AMD’s ZIP, which holds the guide for Zen 2 as a PDF and a spreadsheet of instruction latencies; developer.amd.com no longer serves it. Citations give the page numbers printed on the pages, which in Chapter 2 run six ahead of the PDF’s own. SHA-256 881e216643a1a814; all rights reserved; facts only.
  5. AMD: Software Optimization Guide for AMD Family 17h Processors, 55723, revision 3.01, February 2021. The Wayback Machine’s copy of AMD’s ZIP, which holds the guide as a PDF and a spreadsheet of instruction latencies. It speaks for all of Family 17h but describes models 00h to 0Fh, Zen 1: the source of the Zen and Zen+ page, and cited on the Zen 2 page where Zen 1 differs. Its printed page numbers are those of the PDF. SHA-256 d9c3a7daacab554e; all rights reserved; facts only.
  6. AMD: AMD64 Architecture Programmer's Manual, Volume 2: System Programming, 24593, revision 3.45, July 2026. The time-stamp counter, the performance counters and Instruction-Based Sampling (Chapter 13), the effective frequency interface and boost (Chapter 17) and the TSC ratio of virtual machines (Chapter 15). The URL serves the PDF itself; AMD’s page for the document is https://docs.amd.com/go/en-US/24593_3.45_APM_Vol2_PUB. SHA-256 7257d41d3584822e; all rights reserved; facts only.
  7. AMD: AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions, 24594, revision 3.38, July 2026. The instruction pages of CMOVcc, PREFETCHlevel and RDPRU (Chapter 3) and of RDPMC, RDTSC and RDTSCP (Chapter 4). The URL serves the PDF itself; AMD’s page for the document is https://docs.amd.com/go/en-US/24594_3.38_APM_Vol3_PUB. SHA-256 e18bd39ad0ca19d2; all rights reserved; facts only.
  8. Intel: Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1, 248966, revision 051, October 2026. Chapter 2 describes Golden Cove and its Sapphire Rapids and Alder Lake parts and, in Sections 2.6 and 2.7, the Skylake server and client cores; Chapter 3 gives the general rules with the cases specific to them, Chapters 15 and 17 AVX and AVX-512, Chapter 20 AMX. Citations give the printed page and link the physical page of the PDF. SHA-256 284783f5f6541a60; no derivatives; facts only.
  9. Intel: Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (revision 049), 248966, revision 049, January 2024. The revision before 051, whose Chapter 4 describes Gracemont, the E-core of Alder Lake and Raptor Lake, where 051 describes its successor Crestmont: cited for Gracemont’s own numbers and for what 051 leaves out. Citations give the printed page and link the physical page of the PDF. SHA-256 387e05369b6e2baf; no derivatives; facts only.
  10. Intel: Mitigations for Jump Conditional Code Erratum, 341810, revision 001, November 2019. Intel’s white paper on erratum SKX102 of the Skylake family: what the microcode update changes, its cost, how to measure it, the assembler options that align branches, and the processors affected. Its printed page numbers are those of the PDF. SHA-256 56eaea636d1daf91; no derivatives; facts only.
  11. Intel: Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, 253665, revision 093, September 2026. The basic architecture, which holds the CPUID leaves in this revision: the hybrid bit of leaf 7 and the core type of leaf 1Ah. Citations give the printed page and link the physical page of the PDF. SHA-256 f6ffc430dfa2dada; no derivatives; facts only.
  12. Intel: Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2, 325383, revision 093, September 2026. The instruction reference: what RDTSC, RDTSCP, RDPMC and CPUID wait for and how to order them. Citations give the printed page and link the physical page of the PDF. SHA-256 d137a7887787bbb0; no derivatives; facts only.
  13. Intel: Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 325384, revision 093, September 2026. The system programming guide: the time-stamp counter (Section 20.17), performance monitoring (Chapter 22), APERF and MPERF (Chapter 17) and the TSC of virtual machines (Chapters 27 and 28). Citations give the printed page and link the physical page of the PDF. SHA-256 77919be320f35da2; no derivatives; facts only.
  14. Agner Fog: The microarchitecture of Intel, AMD, and VIA CPUs: An optimization guide for assembly programmers and compiler makers, 23 May 2026. Agner Fog’s measurements and descriptions, cited one fact at a time. Its URL always serves the latest version, so citations give the section and the page of the version of the date above as text instead of linking to the page. SHA-256 75bcd395680df474; no redistribution; facts only.
  15. The LLVM Project: LLVM: the X86 target's processor definitions and scheduling models, commit 85ac56026243 of 20 September 2026 (github.com/llvm/llvm-project, llvm/lib/Target/X86). The release pinned in docker/Dockerfile, whose Clang the instruction reference uses. X86.td names the scheduling model of each -march, and X86Sched*.td hold the models. Apache-2.0 WITH LLVM-exception.
  16. The GCC developers: GCC: the compiler's manual and its x86 tuning tables, commit 04696df09633 of 1 August 2024 (github.com/gcc-mirror/gcc, gcc). The GCC 14.2.0 release, the version of the toolchain image’s gcc-14, whose output the instruction reference shows. doc/invoke.texi and doc/extend.texi describe the options and attributes, and config/i386/x86-tune.def and config/i386/i386-options.cc say which tuning applies to which processor. GPL-3.0 (code) and GFDL-1.3 (manual); facts only.
  17. The Linux kernel developers: Linux: the kernel's documentation, commit c03c1a14507d of 18 October 2026 (github.com/torvalds/linux, Documentation). The release pinned in docker/Dockerfile (v7.3), whose documentation says who may use the performance counters: the perf_event_paranoid sysctl and the rdpmc file of the CPU’s PMU. GPL-2.0; facts only.
  18. The Linux kernel developers: Linux: the kernel's x86 architecture code, commit c03c1a14507d of 18 October 2026 (github.com/torvalds/linux, arch/x86). The release of linux-docs (v7.3). include/asm/intel-family.h names the cores of each Intel processor model and the core types of CPUID leaf 1Ah, include/asm/cpufeatures.h the hybrid bit of CPUID leaf 7. GPL-2.0; facts only.
  19. Intel: Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 2, 356477, revision 051, October 2026. Volume 1’s companion for the generations its revision history moved out: Haswell (Chapter 1), Sandy Bridge and Ivy Bridge (Chapter 2), Intel Core and Enhanced Intel Core (Chapter 3), Nehalem (Chapter 4), Knights Landing (Chapter 5) and earlier Atom cores (Chapter 6). Citations give the printed page and link the physical page of the PDF. SHA-256 65cd29f29db4a929; no derivatives; facts only.
  20. AMD: Software Optimization Guide for AMD Family 15h Processors, 47414, revision 3.08, January 2014. The Wayback Machine’s copy of AMD’s guide for Family 15h, the file that amd.com served from 2014 on. Revision 3.08 describes models 00h to 4Fh: Bulldozer, Piledriver and Steamroller, but not Excavator. Its printed page numbers are those of the PDF. SHA-256 4326f8ab74179781; all rights reserved; facts only.
  21. AMD: Software Optimization Guide for AMD Family 16h Processors, 52128, revision 1.1, March 2013. The Wayback Machine’s copy of AMD’s ZIP, which holds the guide as a PDF and a spreadsheet of instruction latencies; amd.com no longer serves it, and every copy the Wayback index holds, from 2013 on, is this file. Revision 1.1 is the guide’s only release: it describes Jaguar, from before Puma, and not Bobcat of Family 14h. Its printed page numbers are those of the PDF. SHA-256 7199b67120a49ea8; all rights reserved; facts only.
  22. x86-64.net: Measurements of an AMD EPYC 9645 (Zen 5) in a KVM guest, run of 19 October 2026 (tools/optimize/measure/fixtures/zen5-epyc-9645.json). One run of the site’s measuring probe (make measure) on one virtual CPU of a KVM guest whose host has an EPYC 9645 (CPUID family 1Ah, model 11h, stepping 0), with 101 samples of each result; other jobs kept the guest’s load average between 20 and 24. The measuring chapter describes the method. SHA-256 7c9da999b80313eb; our own measurement.