x86-64 microarchitecture levels
Four cumulative feature sets that say how modern an x86-64 processor is. Compilers, the glibc dynamic loader and Linux distributions all use them.
The 64-bit x86 architecture that AMD introduced in 2003 guarantees SSE2 and nothing newer. Processors kept adding instructions after that, from SSE3 through AVX-512, but a program built for plain “x86-64” could not assume any of them without checking at run time.
In 2020 the x86-64 psABI, the document that defines the System V calling convention and object format for x86-64, gave names to three sets of features on top of that baseline. Each set groups instructions that Intel and AMD processors shipped together.
| Level | Adds | First Intel | First AMD |
|---|---|---|---|
| x86-64-v1 | CMOV, CX8, FPU, FXSR, MMX, OSFXSR, SCE, SSE, SSE2 | NetBurst (Prescott, Nocona) (2004) | K8 (Hammer) (2003) |
| x86-64-v2 | CMPXCHG16B, LAHF-SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3 | Nehalem (2008) | Bulldozer (2011) |
| x86-64-v3 | AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, OSXSAVE | Haswell (2013) | Excavator (2015) |
| x86-64-v4 | AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL | Skylake-SP (2017) | Zen 4 (2022) |
The levels are cumulative. A processor supports x86-64-v3 only if it has every feature of v3, v2 and the baseline; one missing feature is enough to drop it to a lower level.
Where the levels are used
- Compilers
- GCC 11 and Clang 12 added
-march=x86-64-v2,-march=x86-64-v3and-march=x86-64-v4. Go 1.18 addedGOAMD64=v1tov4(the default is v1). Rust uses the same names through-C target-cpu=x86-64-v3. - The dynamic loader
- Since glibc 2.33, the dynamic loader looks for optimized copies of
shared libraries in
glibc-hwcaps/x86-64-v2,x86-64-v3andx86-64-v4subdirectories of the library path, and loads the highest one the processor supports. - Distributions
- A distribution can build all of its packages for a level, which makes that level the minimum a machine needs to run it.
The operating system has a say
Two of the listed features, OSFXSR and OSXSAVE, describe the operating
system rather than the processor. The wide AVX registers can only be
used once the OS has enabled saving them on context switches, so the
psABI counts v3 and v4 as available only when the processor supports
them and the OS has enabled their state (checked with xgetbv).
Every current operating system enables this. It matters inside virtual machines: a hypervisor decides which features the guest sees, so a VM can report a lower level than the machine it runs on.
Beyond v4: AVX10 and APX
The psABI defines no level after x86-64-v4. Newer extensions are
enabled one by one instead; for example, GCC 15 enables AVX10.2 with
-mavx10.2 and APX with -mapxf.
Levels are not generations
A level is a feature set, not a date. Intel’s hybrid laptop and desktop processors from Alder Lake (2021) to Panther Lake (2026) are x86-64-v3, while Ice Lake laptops from 2019 are x86-64-v4. A Pentium Silver from 2020 is x86-64-v2, and Pentium and Celeron models of Haswell through Comet Lake are x86-64-v2 while the Core models of the same generation are v3. Check the model, not the year.
- x86-64-v1: The x86-64 baseline (x86-64-v1) is the original 64-bit x86 feature set from 2003. Features, CPUIDs, Linux flags and which processors stop at it.
- x86-64-v2: x86-64-v2 adds SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CMPXCHG16B and LAHF/SAHF. Features, CPUID bits, Linux flags and which processors support it.
- x86-64-v3: x86-64-v3 adds AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT and MOVBE. Features, CPUID bits, Linux flags and which processors support it, including the exceptions.
- x86-64-v4: x86-64-v4 adds AVX-512 F, BW, CD, DQ and VL. Features, CPUID bits, Linux flags and which processors support it, including Intel's hybrid chips that do not.