x86-64.net

Optimizing code for Intel Darkmont

The numbers Intel’s architects have published for the E-core of Clearwater Forest, which Linux calls Darkmont, against the Crestmont core of Sierra Forest. They come from conference slides and are Intel’s projections, so this page has numbers rather than rules; for rules the nearest page is Crestmont’s.

Microarchitecture
Intel Clearwater Forest
Claims
14, 1 with a source that differs

The core in numbers

Processors
Linux’s table of Intel models names Darkmont as the core of Clearwater Forest (Xeon 6+) and the E-core of Panther Lake. The slides speak only of “Clearwater Forest E-core” and name neither Darkmont nor Panther Lake: the link between them is Linux’s, and every number here is stated for Clearwater Forest. No source here says that Panther Lake’s E-cores have these numbers. [Linux 7.3 x86, include/asm/intel-family.h, line 194; Linux 7.3 x86, include/asm/intel-family.h, line 154; Soltis and Robinson, Hot Chips 2025, Slide 6, page 6]
Sources
This page rests on the slide deck of a talk at Hot Chips 2025 by Don Soltis and Stephen Robinson, Intel Fellows, hosted by the conference and not by Intel. It has no optimization rules from Intel, and its numbers are Intel’s “architectural projections as of August 2025”; none of them measures a shipping part. Revision 051 of Intel’s manual and Agner Fog’s manual of 2026-05-23 do not cover the core; the manual’s chapter on these cores ends at Crestmont. [Soltis and Robinson, Hot Chips 2025, Slides 1 and 11, pages 1 and 11; Intel 248966, Section 4.1, page 4-1; Agner Fog, Contents and Chapter 13, page 173]
Compiler models
LLVM has no model of this core: -march=clearwaterforest and -march=pantherlake schedule with its Alder Lake P-core model, the one Crestmont’s targets use as well. [LLVM 23.1.2, X86.td, line 2133; LLVM 23.1.2, X86.td, line 2140]
Width
9 instructions decoded a cycle, by three decoders of three each, the slide’s 50% over Sierra Forest; 8 micro-ops allocated and 16 retired, its 1.6 and 2 times. [Soltis and Robinson, Hot Chips 2025, Slides 7 and 8, pages 7 and 8]
In flight
416 entries in the out-of-order window, which the slide calls 1.6 times Sierra Forest’s; Crestmont’s 256 makes that 1.625 times. [Soltis and Robinson, Hot Chips 2025, Slide 8, page 8]
Ports
26, the slide’s 1.5 times; Crestmont has 17. The deck does not list them. [Soltis and Robinson, Hot Chips 2025, Slides 8 and 9, pages 8 and 9]
L1 instruction cache
64 KB, as on Crestmont, with a length decoder that works on demand. [Soltis and Robinson, Hot Chips 2025, Slide 7, page 7]
L2 cache
4 MB shared by a module of four cores, at 17 cycles; 400 GB/s, twice Sierra Forest’s. The diagram marks 200 GB/s per core and 35 GB/s at the fabric interface. [Soltis and Robinson, Hot Chips 2025, Slide 11, page 11]
L2 misses in flight
128, twice Crestmont’s 64. [Soltis and Robinson, Hot Chips 2025, Slide 10, page 10]

Execution and memory

Against Sierra Forest, the slide doubles integer and vector execution and store address generation, and gives load address generation 1.5 times. It does not count the units, so these are ratios only. [Soltis and Robinson, Hot Chips 2025, Slide 9, page 9]

Three loads a cycle, 1.5 times Sierra Forest’s, and two stores, unchanged. Intel adds that loads issue earlier, which it says may reduce their latency, without a number. [Soltis and Robinson, Hot Chips 2025, Slide 10, page 10]

Intel claims more accurate branch prediction, from deeper history and larger tables, and prefetchers at every cache level, without sizes for any of them. [Soltis and Robinson, Hot Chips 2025, Slides 7 and 10, pages 7 and 10]

In LLVM, -march=clearwaterforest adds to -march=sierraforest AVX-VNNI-INT16, SHA-512, SM3, SM4, USER_MSR and the code prefetches, and drops Key Locker’s wide instructions. -march=pantherlake has none of USER_MSR and the code prefetches, so the feature lists of the two parts differ. [LLVM 23.1.2, X86.td, line 1489; LLVM 23.1.2, X86.td, line 1462]

Measuring

Intel projects 17% more instructions per cycle than Sierra Forest, an estimate on SPECint rate 2017, from the same projections of August 2025; no measurement of ours stands behind it. [Soltis and Robinson, Hot Chips 2025, Slide 11, page 11]

Sources

  1. The Linux kernel developers: Linux: the kernel's x86 architecture code, commit c03c1a14507d of 18 October 2026 (github.com/torvalds/linux, arch/x86). The release of linux-docs (v7.3). include/asm/intel-family.h names the cores of each Intel processor model and the core types of CPUID leaf 1Ah, include/asm/cpufeatures.h the hybrid bit of CPUID leaf 7. GPL-2.0; facts only.
  2. Don Soltis and Stephen Robinson, Intel: Clearwater Forest: the Next Generation Intel Xeon Processor with Efficiency Cores (Hot Chips 2025), August 2025. The slides of a talk by two Intel Fellows, hosted by the Hot Chips conference, not by Intel. They describe the E-core of Clearwater Forest with Intel’s projections as of August 2025, not measurements of a shipping part, and give no rules for code. Citations give the slide, the physical page of the PDF. SHA-256 c6b42af22b12d991; all rights reserved; facts only.
  3. Intel: Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1, 248966, revision 051, October 2026. Chapter 2 describes Golden Cove and its Sapphire Rapids and Alder Lake parts and, in Sections 2.6 and 2.7, the Skylake server and client cores; Chapter 3 gives the general rules with the cases specific to them, Chapters 15 and 17 AVX and AVX-512, Chapter 20 AMX. Citations give the printed page and link the physical page of the PDF. SHA-256 284783f5f6541a60; no derivatives; facts only.
  4. Agner Fog: The microarchitecture of Intel, AMD, and VIA CPUs: An optimization guide for assembly programmers and compiler makers, 23 May 2026. Agner Fog’s measurements and descriptions, cited one fact at a time. Its URL always serves the latest version, so citations give the section and the page of the version of the date above as text instead of linking to the page. SHA-256 75bcd395680df474; no redistribution; facts only.
  5. The LLVM Project: LLVM: the X86 target's processor definitions and scheduling models, commit 85ac56026243 of 20 September 2026 (github.com/llvm/llvm-project, llvm/lib/Target/X86). The release pinned in docker/Dockerfile, whose Clang the instruction reference uses. X86.td names the scheduling model of each -march, and X86Sched*.td hold the models. Apache-2.0 WITH LLVM-exception.