Optimizing code for Intel Lion Cove

Intel claims a prediction block up to 8 times as large, wider fetch and more decode bandwidth, a micro-op cache of greater capacity and read bandwidth, and a larger micro-op queue. None of these comes with a size. The diagram labels the decoders 8 wide and the micro-op cache 12 wide. [Intel Lion Cove deck, Slide 12, page 12]

The deck gives the micro-op queue no size. LLVM’s model sizes the loop buffer at 200 micro-ops, against the 192 Intel’s manual gives Redwood Cove. It is the only number here for the queue, and it comes from a compiler’s model. [LLVM 23.1.2, X86SchedLunarlakeP.td, line 29; Intel Lion Cove deck, Slide 12, page 12; Intel 248966, Section 2.1.1, page 2-1]

Integer and vector code have separate renaming and schedulers, which Intel presents as a way to grow each side alone and to save power in code that uses only one. [Intel Lion Cove deck, Slide 13, page 13]

LLVM’s model gives the integer scheduler 110 entries, the vector one 180, store data 48 and memory 72. The deck has no scheduler sizes. [LLVM 23.1.2, X86SchedLunarlakeP.td, line 80; LLVM 23.1.2, X86SchedLunarlakeP.td, line 86; LLVM 23.1.2, X86SchedLunarlakeP.td, line 91; LLVM 23.1.2, X86SchedLunarlakeP.td, line 97]

Six integer ALUs, up from the deck’s previous value of 5; three jump units and three shift units, up from 2 each; three 64-bit multipliers, up from 1. The diagram puts jumps on P0, P2 and P4 and shifts and multipliers on P1, P3 and P5. [Intel Lion Cove deck, Slides 13 and 15, pages 13 and 15]

Four 256-bit SIMD ALUs, up from the deck’s previous value of 3; two 256-bit FMA units at 4 cycles; two 256-bit floating-point dividers, up from 1, which Intel says also have a better latency and throughput, without numbers. [Intel Lion Cove deck, Slide 16, page 16]

LLVM’s model agrees on FMA at 4 cycles and gives floating-point multiplication 3 and addition 2, the first on V0 and V1 and the second on V2 and V3. [LLVM 23.1.2, X86SchedLunarlakeP.td, line 461; LLVM 23.1.2, X86SchedLunarlakeP.td, line 500; LLVM 23.1.2, X86SchedLunarlakeP.td, line 305]

In LLVM, -march=lunarlake and -march=arrowlake-s have the same instructions, and -march=arrowlake lacks AVX-VNNI-INT16, SHA-512, SM3 and SM4 of them. LLVM’s model has no 512-bit FMA, so the 512-bit read width of the L0 cache is not a sign of AVX-512 in these sources. [LLVM 23.1.2, X86.td, line 1437; LLVM 23.1.2, X86.td, line 1452; LLVM 23.1.2, X86SchedLunarlakeP.td, line 485]

The deck estimates that a core built without Hyper-Threading gets 15% better performance per power and 10% better performance per area than one built with it, on one thread. LLVM’s comment says Lion Cove removed it, and the Core Ultra 9 285K has 24 cores and 24 threads. The deck compares hypothetical cores and does not say which parts lack it. [Intel Lion Cove deck, Slide 7, page 7, and slide 25, page 25; LLVM 23.1.2, X86SchedLunarlakeP.td, line 28; Intel 200S briefing, Slide 10, page 10]

From the cache numbers, a load from data outside the first 48 KB and inside the next level takes 9 cycles where Redwood Cove’s L2 takes 16, while a load served by Lion Cove’s 17-cycle L2 is one cycle slower. These are the slide’s numbers, not a measurement. [Intel Lion Cove deck, Slide 17, page 17]

Three store address units, up from the deck’s previous value of 2. The deck gives three load ports on its diagram and says nothing of how many stores can finish a cycle. [Intel Lion Cove deck, Slides 12 and 18, pages 12 and 18]

LLVM’s model takes integer loads at 4 cycles, as the deck’s L0 does, and vector loads at 6, with a comment that this value comes from its Alder Lake model. [LLVM 23.1.2, X86SchedLunarlakeP.td, line 22; LLVM 23.1.2, X86SchedLunarlakeP.td, line 110]

Intel estimates 14% more instructions per cycle than Redwood Cove, at equal frequency, over a set of benchmarks it names. Its briefing gives Arrow Lake’s desktop P-core 9% over Raptor Cove. Both are Intel’s own figures, without our measurements. [Intel Lion Cove deck, Slide 19, page 19, and slide 25, page 25; Intel 200S briefing, Slide 5, page 5]

The core’s clock steps in intervals of 16.67 MHz, where the slide’s earlier design stepped by 100 MHz, so its frequency need not be a multiple of 100 MHz. [Intel Lion Cove deck, Slide 10, page 10]

Ten general-purpose counters per core against eight on Golden and Redwood Cove, and 12 architectural events, with fewer restrictions on which event runs on which counter: the measuring chapter says how to use them. [Intel 325384, Section 22.3.11.1, Table 22-57, pages 22-81 and 22-82]