Optimizing code for Intel Tremont

A predictor that covers 32 bytes a cycle sends the block of code after each taken branch to the other of two decoders of three instructions each. A younger block may finish decoding first; each cluster fills its own queue of micro-ops, and allocation reads both and puts them back in program order. [Intel 248966, Sections 4.2.1 and 4.2.2, pages 4-12 and 4-13]

Tremont has no hardware to balance the two clusters, so a long stretch of code without a taken branch, such as an unrolled floating-point loop, decodes on one cluster only. Intel suggests an unconditional jmp to the next instruction every 16 to 32 instructions; the later cores split such stretches by themselves. [Intel 248966, Section 4.2.2, page 4-13]

The decoders find instruction boundaries from marks kept with the instruction cache; a second-level cache of these marks holds 128 KB, twice Goldmont Plus’s. [Intel 248966, Section 4.2.2, page 4-13; Agner Fog, Section 16.2, page 188]

Each cluster decodes as Goldmont Plus did, so an instruction should carry at most 4 bytes of prefixes and escape bytes; Agner Fog found long delays beyond that, and for some combinations of three, such as F3 with 66 or a REX prefix. A prefix that changes the length of an immediate costs nothing, and LLVM keeps 16-bit immediates for this core. [Intel 248966, Section 4.2.2, page 4-13; Agner Fog, Section 16.2, page 188; LLVM 23.1.2, X86.td, line 862; LLVM 23.1.2, X86.td, line 1384]

The decoders turn most instructions into one micro-op, one that loads and computes or loads, computes and stores included. Instructions of three or more micro-ops, and some of two, come from the microcode ROM and take at least 4 cycles to decode. [Agner Fog, Section 16.2, page 188]

A loop buffer replays decoded micro-ops of small loops, which can then run slightly faster than three instructions a cycle; it is larger than Goldmont’s, which held 29 instructions, but its size is not known. [Agner Fog, Sections 16.1 and 16.4, pages 188 and 189]

Tremont fuses no pair of instructions into one micro-op, not even a compare and the branch after it, and LLVM’s tuning for it expects no fusion. [Agner Fog, Section 16.5, page 189; LLVM 23.1.2, X86.td, line 1379; LLVM 23.1.2, X86.td, line 1393]

LLVM pads code for Tremont with NOPs of up to 10 bytes, its default when a processor’s tuning names no other length; it uses 7 for Silvermont and 15 for the later E-cores. [LLVM 23.1.2, MCTargetDesc/X86AsmBackend.cpp, line 966; LLVM 23.1.2, X86.td, line 1379; LLVM 23.1.2, X86.td, line 1345; LLVM 23.1.2, X86.td, line 1432]

Intel enlarged the branch predictor, improved its prediction of conditional and indirect branches from the path taken to them, and added a return stack buffer that is updated only by retired calls and returns; it gives no sizes. [Intel 248966, Sections 4.2 and 4.2.2, pages 4-10 and 4-13]

The branch target buffer works on aligned 16-byte blocks of code: a taken jump runs one a cycle when it is the only one in its block, but several taken jumps in one block take several cycles each, up to 7. Not-taken conditional jumps run one a cycle. [Agner Fog, Section 16.3, Table 16.1, pages 188 and 189]

Jumps execute only on port 08; two decode clusters let two branches be decoded at once, which shortens the delay after a misprediction, and LLVM’s model counts 10 cycles for one. [Intel 248966, Section 4.2.3, Table 4-2, page 4-14; Agner Fog, Section 16.2, page 188; LLVM 23.1.2, X86ScheduleSLM.td, line 20]

Three ALU ports run simple integer operations, three a cycle; shifts go to port 00 only, and multiplication, division, popcnt, crc32 and the bit operations to port 01 only. [Intel 248966, Section 4.2.3, Table 4-2, page 4-14]

An lea with two of base, index and displacement and no scaled index runs on any ALU port in one micro-op; one with all three is two micro-ops, the one using the index on port 02, and a cycle longer; a scaled index without displacement keeps it one micro-op, but on port 02 only. LLVM’s tuning marks some lea forms as slow on this core. [Intel 248966, Section 4.2.3, Table 4-2, page 4-14; LLVM 23.1.2, X86.td, line 574; LLVM 23.1.2, X86.td, line 1381]

xor of a register with itself is known not to depend on the register’s old value, for 32-bit and 64-bit, MMX and XMM registers; sub of a register from itself and other idioms are not. [Agner Fog, Section 16.6, page 189]

A move between 32-bit, 64-bit or XMM registers can be done by renaming, at most one a cycle, and in a chain of moves only the first; Agner Fog found that it often fails, and that MMX moves are never eliminated. [Agner Fog, Section 16.7, page 189]

Writing a byte or word of a register waits for the register’s other bits, and reading the flags after an instruction that writes only some of them costs a cycle more. LLVM avoids inc and dec, which leave the carry flag alone, in favour of add and sub for this core. [Agner Fog, Section 16.8, page 190; LLVM 23.1.2, X86.td, line 586; LLVM 23.1.2, X86.td, line 1382]

LLVM’s tuning treats push, pop and call with a memory operand as slow on this core and loads the operand into a register first. [LLVM 23.1.2, X86.td, line 554; LLVM 23.1.2, X86.td, line 1380]

LLVM’s tuning prefers movbe to a load and bswap, or to bswap and a store, on this core. [LLVM 23.1.2, X86.td, line 857; LLVM 23.1.2, X86.td, line 1383]

LLVM’s tuning for Tremont, as for Goldmont Plus, does not make popcnt wait for its destination register’s old value, which its Goldmont tuning does. [LLVM 23.1.2, X86.td, line 1370; LLVM 23.1.2, X86.td, line 1379; LLVM 23.1.2, X86.td, line 590]

Vectors are 128 bits wide and stop at SSE4.2: Tremont has no AVX of any kind, so code built for x86-64-v3 does not run on it. LLVM’s -march=tremont enables SSE4.2 and nothing wider. [Agner Fog, Chapter 16 and Section 16.11, pages 188 and 190; LLVM 23.1.2, X86.td, line 1333]

Two vector ports run integer and floating-point operations: port 20 takes the multiplications, divisions, shifts, integer multiplications, conversions and GFNI, port 21 the floating-point additions; both run simple integer operations and shuffles. Port 29 handles the data of vector stores. [Intel 248966, Section 4.2.3, Table 4-2, page 4-14]

Tremont has two AES units, one on each vector port, so two AES rounds can start each cycle. [Intel 248966, Sections 4.2 and 4.2.3, Table 4-2, pages 4-11 and 4-14]

Intel improved the SHA extensions on Tremont: the round instructions run on port 20 and the message instructions on port 21, so the two can overlap. [Intel 248966, Sections 4.2 and 4.2.3, Table 4-2, pages 4-11 and 4-14]

Tremont adds the Galois-field instructions, for ciphers, error correction and bit-matrix multiplication, which run on port 20, and speeds up pclmulqdq; Intel gives no numbers. [Intel 248966, Sections 4.2, 4.2.3 and 4.2.5, pages 4-11, 4-14 and 4-15]

A value that moves between the integer and the vector units costs 4 cycles; within the vector unit, mixing integer and floating-point instructions on the same data adds no delay, and LLVM’s tuning expects none. [Agner Fog, Section 16.7, page 189; LLVM 23.1.2, X86.td, line 665; LLVM 23.1.2, X86.td, line 1386]

An operation with a subnormal input or result, or one that underflows, takes 100 to 200 cycles unless MXCSR has both FTZ and DAZ set. [Agner Fog, Section 16.7, page 190]

Two loads, two stores, or a load and a store a cycle, twice Goldmont Plus’s rate for each, with separate ports for the data of integer and vector stores. [Intel 248966, Sections 4.2 and 4.2.4, pages 4-11 and 4-14]

A store forwards to a later load of the same or a smaller size that starts at the same address, 5 to 6 cycles from store to load, and on Tremont also to two loads of its two halves. Other overlaps fail and cost 3 to 7 cycles more; a forwarded store that crosses a cache line costs 6 more. [Agner Fog, Section 16.10, page 190]

Agner Fog saw no cache bank conflicts, but a false dependence between addresses a multiple of 4 KB apart. [Agner Fog, Section 16.9, page 190]

Tremont adds umonitor, umwait and tpause, which let a spin loop in user mode wait at low power, clwb, cldemote, movdiri and movdir64b, and detection of split locks; Intel notes that products may differ. GCC’s -march=tremont enables all of them. [Intel 248966, Section 4.2.5, page 4-15; Intel 253665, Chapter 5, Table 5-2, pages 5-3 and 5-4; GCC 14.2, config/i386/i386.h, line 2410; GCC 14.2, config/i386/i386.h, line 2411]

Sampling with PEBS has no skid on general counter 0 and the fixed counter of instructions, so a sample names the instruction that caused it; since the sample is taken at the event after the overflow, Intel suggests counting from a prime number less one. [Intel 248966, Section 4.2.5, page 4-15]

Tremont is the first Atom core with Intel’s Speed Shift, and shares much of its power management with Ice Lake clients; the rest depends on the product. [Intel 248966, Section 4.2.6, page 4-15]

Lakefield pairs one Sunny Cove core with Tremont cores under one model number, 8Ah, so the model cannot tell them apart. CPUID marks a hybrid part with bit 15 of leaf 7’s EDX, and leaf 1Ah gives the type of the core a thread runs on in bits 31:24 of EAX: 20h for an Atom core, 40h for a Core. [Linux 7.2 x86, include/asm/intel-family.h, line 136; Linux 7.2 x86, include/asm/cpufeatures.h, line 432; Intel 253665, Section 21.3, Table 21-21, page 21-29; Intel 253665, Section 21.3, Table 21-63, page 21-66]

Beyond its 1.5 MB L2, Intel’s manuals say nothing of what Lakefield’s mix of cores means for code: the optimization manual’s section on hybrid processors describes Alder Lake and the cores after it. [Intel 248966, Section 4.2.4, page 4-14; Intel 248966, Section 2.3, page 2-6]