x86-64-v2
Adds SSE3 through SSE4.2, POPCNT, CMPXCHG16B and LAHF/SAHF. Intel first reached it with Nehalem in 2008, AMD with Bulldozer in 2011.
x86-64-v2 collects the SIMD and integer additions from the years after
x86-64 appeared: SSE3, SSSE3, SSE4.1 and SSE4.2, the POPCNT
population count, 16-byte compare-and-exchange and LAHF/SAHF in
64-bit mode.
| Feature | What it provides | Enumerated by | Linux flag | Example |
|---|---|---|---|---|
| CMPXCHG16B | 16-byte compare-and-exchange, used for lock-free algorithms. | CPUID.01H:ECX[13] | cx16 | cmpxchg16b |
| LAHF-SAHF | LAHF and SAHF in 64-bit mode. | CPUID.80000001H:ECX[0] | lahf_lm | lahf |
| POPCNT | Population count (number of set bits). | CPUID.01H:ECX[23] | popcnt | popcnt |
| SSE3 | SSE3, shown as pni ("Prescott New Instructions") by Linux. | CPUID.01H:ECX[0] | pni | addsubpd |
| SSE4.1 | SSE4.1 blends, rounding, dot products and more. | CPUID.01H:ECX[19] | sse4_1 | blendpd |
| SSE4.2 | SSE4.2 string comparison and CRC32. | CPUID.01H:ECX[20] | sse4_2 | pcmpestri |
| SSSE3 | Supplemental SSE3, including byte shuffles. | CPUID.01H:ECX[9] | ssse3 | phaddd |
What it gives software
SSE4.2 adds fast string comparison (PCMPESTRI and relatives) and a
CRC32 instruction, POPCNT counts bits in one instruction, and
CMPXCHG16B makes lock-free algorithms on pointer-plus-counter pairs
possible. With -march=x86-64-v2, compilers use all of these without
run-time checks.
Processors at this level
- Intel Core (client)
- Nehalem (2008), Westmere (2010), Sandy Bridge (2011), Ivy Bridge (2012)
- Intel Atom and E-cores
- Silvermont (2013), Airmont (2015), Goldmont (2016), Goldmont Plus (2017), Tremont (2020)
- AMD (high performance)
- Bulldozer (2011), Piledriver (2012), Steamroller (2014)
- AMD (low power)
- Jaguar (2013), Puma (2014)
- Zhaoxin
- LuJiaZui (2019)
Two popular families narrowly miss it. Intel’s Core 2 (Merom, Penryn)
lacks SSE4.2 and POPCNT, and AMD’s K10 (Phenom, Athlon II) lacks
SSSE3 and SSE4.1, so both are baseline processors.
Who requires it
| Name | Minimum | Since | Notes | Checked |
|---|---|---|---|---|
| .NET Runtime | x86-64-v2 | .NET 11 (2026) | Older processors fail with “The current CPU is missing one or more of the baseline instruction sets”. ReadyToRun code in .NET 11 targets x86-64-v3 on Windows and Linux and falls back to the JIT on older processors. Source | |
| Red Hat Enterprise Linux 9 Operating system | x86-64-v2 | 9.0 (2022) | Source | |
| SUSE Linux Enterprise Server 16 Operating system | x86-64-v2 | 16.0 (2025) | The release notes add that QEMU guests need -cpu host (or another model with x86-64-v2 features) to boot. Source | |
| Windows 11 Operating system | x86-64-v2 | 24H2 (2024) | Microsoft states that Windows 11 requires the x86-64-v2 instructions. Starting with version 24H2, Windows uses SSE4.2 and POPCNT and does not boot on processors without them. Source 1, Source 2 | |
| openSUSE Leap 16 Operating system | x86-64-v2 | 16.0 (2025) | Source |
Building for it
gcc -march=x86-64-v2 ... # GCC 11+, Clang 12+
GOAMD64=v2 go build ... # Go 1.18+
RUSTFLAGS="-C target-cpu=x86-64-v2" cargo build ...
Shared libraries built this way can be installed in a
glibc-hwcaps/x86-64-v2 subdirectory of the library path. glibc 2.33
and later load them only on processors that support the level.