x86-64-v3
Adds AVX, AVX2, FMA, BMI1, BMI2, F16C, LZCNT and MOVBE, the feature set of Intel’s Haswell (2013) and AMD’s Excavator (2015). Distributions are now moving their baseline to it.
x86-64-v3 brings 256-bit SIMD: AVX for floating point and AVX2 for integers, fused multiply-add, and the BMI1 and BMI2 bit-manipulation instructions. It also requires the operating system to have enabled the AVX register state (OSXSAVE).
| Feature | What it provides | Enumerated by | Linux flag | Example |
|---|---|---|---|---|
| AVX | 256-bit floating-point SIMD with VEX encoding. | CPUID.01H:ECX[28] | avx | vzeroall |
| AVX2 | 256-bit integer SIMD, gathers and permutes. | CPUID.(EAX=07H,ECX=0):EBX[5] | avx2 | vpermd |
| BMI1 | Bit manipulation instructions, group 1. | CPUID.(EAX=07H,ECX=0):EBX[3] | bmi1 | andn |
| BMI2 | Bit manipulation instructions, group 2. | CPUID.(EAX=07H,ECX=0):EBX[8] | bmi2 | bzhi |
| F16C | Half-precision float conversion. | CPUID.01H:ECX[29] | f16c | vcvtph2ps |
| FMA | Fused multiply-add (three-operand FMA3). | CPUID.01H:ECX[12] | fma | vfmadd132pd |
| LZCNT | Leading zero count, shown as abm by Linux. | CPUID.80000001H:ECX[5] | abm | lzcnt |
| MOVBE | Load or store with a byte swap. | CPUID.01H:ECX[22] | movbe | movbe |
| OSXSAVE | The OS has enabled XSAVE, so AVX state is saved across context switches. | CPUID.01H:ECX[27]OS support; hardware feature: XSAVE | not shown | xgetbv |
What it gives software
Compilers can vectorize loops with 256-bit registers instead of
128-bit ones, fuse multiplies and adds into one rounded operation, and
use instructions like ANDN, BZHI, SHLX and LZCNT for bit
manipulation. Libraries such as compression, hashing and math code
often see the largest gains.
Processors at this level
- Intel Core (client)
- Haswell (2013), Broadwell (2014), Skylake (2015), Kaby Lake (2016), Coffee Lake (2017), Comet Lake (2019), Alder Lake (2021), Raptor Lake (2022), Meteor Lake (2023), Arrow Lake (2024), Lunar Lake (2024), Panther Lake (2026)
- Intel Xeon (server)
- Sierra Forest (2024), Clearwater Forest (2026)
- Intel Atom and E-cores
- Gracemont (2021)
- Intel Xeon Phi
- Knights Landing (2016), Knights Mill (2017)
- AMD (high performance)
- Excavator (2015), Zen (2017), Zen+ (2018), Zen 2 (2019), Zen 3 (2020)
- Hygon
- Dhyana (2018)
- Zhaoxin
- Century Avenue (Shijidadao) (2023)
Watch out for
- Intel’s Atom line reached x86-64-v3 only with Gracemont (2021). Earlier low-power chips sold as Pentium Silver and Celeron, up to Tremont, are x86-64-v2.
- AMD’s Bulldozer, Piledriver and Steamroller have AVX but not AVX2, so they are x86-64-v2; Excavator is the first AMD core at v3.
- Virtual machines often hide AVX from the guest unless configured otherwise.
Who requires it
Building for it
gcc -march=x86-64-v3 ... # GCC 11+, Clang 12+
GOAMD64=v3 go build ... # Go 1.18+
RUSTFLAGS="-C target-cpu=x86-64-v3" cargo build ...
A binary built this way stops with an illegal-instruction error
(SIGILL) on processors below the level, often at the first
vectorized loop. Installing an optimized copy of a shared library in
glibc-hwcaps/x86-64-v3 avoids that: glibc 2.33 and later load it only
where it can run.