x86-64-v4
Adds AVX-512 Foundation with the BW, CD, DQ and VL subsets. Intel first reached it with Skylake-SP in 2017, AMD with Zen 4 in 2022.
x86-64-v4 is AVX-512: 512-bit vector registers (32 of them), mask registers for per-element predication, and the subsets for byte and word elements (BW), doublewords and quadwords (DQ), conflict detection (CD) and the same instructions on 128- and 256-bit vectors (VL).
| Feature | What it provides | Enumerated by | Linux flag | Example |
|---|---|---|---|---|
| AVX512F | AVX-512 foundation. | CPUID.(EAX=07H,ECX=0):EBX[16] | avx512f | kmovw |
| AVX512BW | AVX-512 byte and word instructions. | CPUID.(EAX=07H,ECX=0):EBX[30] | avx512bw | vdbpsadbw |
| AVX512CD | AVX-512 conflict detection. | CPUID.(EAX=07H,ECX=0):EBX[28] | avx512cd | vplzcntd |
| AVX512DQ | AVX-512 doubleword and quadword instructions. | CPUID.(EAX=07H,ECX=0):EBX[17] | avx512dq | vpmullq |
| AVX512VL | AVX-512 instructions on 128- and 256-bit vectors. | CPUID.(EAX=07H,ECX=0):EBX[31] | avx512vl | n/a |
Processors at this level
- Intel Core (client)
- Cannon Lake (2018), Ice Lake (client) (2019), Tiger Lake (2020), Rocket Lake (2021), Nova Lake (announced)
- Intel Xeon (server)
- Skylake-SP (2017), Cascade Lake (2019), Cooper Lake (2020), Ice Lake (server) (2021), Emerald Rapids (2023), Sapphire Rapids (2023), Granite Rapids (2024), Diamond Rapids (announced)
- AMD (high performance)
- Zen 4 (2022), Zen 5 (2024), Zen 6 (announced)
Watch out for
- Intel’s hybrid client processors, from Alder Lake (2021) to Panther Lake (2026), do not support AVX-512 and are x86-64-v3. Intel has confirmed AVX10.2 for Nova Lake, which brings 512-bit vectors back to its client processors.
- The Xeon Phi processors Knights Landing and Knights Mill implement AVX-512 Foundation and CD but not BW, DQ or VL, so they are x86-64-v3.
- AMD’s Zen 4 executes 512-bit operations as two 256-bit halves, and Zen 5 has full-width 512-bit units in most models. Both are x86-64-v4: the level is about which instructions exist, not how fast they run.
Building for it
gcc -march=x86-64-v4 ... # GCC 11+, Clang 12+
GOAMD64=v4 go build ... # Go 1.18+
RUSTFLAGS="-C target-cpu=x86-64-v4" cargo build ...
The psABI defines no level after x86-64-v4. Later extensions are
enabled individually; GCC 15, for example, has -mavx10.2 for AVX10.2
and -mapxf for APX.